Lines Matching full:g
83 const struct msm_pingroup *g) \
85 return readl(pctrl->regs[g->tile] + g->name##_reg); \
88 const struct msm_pingroup *g) \
90 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
174 const struct msm_pingroup *g; in msm_pinmux_set_mux() local
179 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
180 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); in msm_pinmux_set_mux()
182 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
183 if (g->funcs[i] == function) in msm_pinmux_set_mux()
187 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
192 val = msm_readl_ctl(pctrl, g); in msm_pinmux_set_mux()
194 val |= i << g->mux_bit; in msm_pinmux_set_mux()
195 msm_writel_ctl(val, pctrl, g); in msm_pinmux_set_mux()
207 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio() local
210 if (!g->nfuncs) in msm_pinmux_request_gpio()
214 return msm_pinmux_set_mux(pctldev, g->funcs[0], offset); in msm_pinmux_request_gpio()
227 const struct msm_pingroup *g, in msm_config_reg() argument
237 *bit = g->pull_bit; in msm_config_reg()
241 *bit = g->od_bit; in msm_config_reg()
245 *bit = g->drv_bit; in msm_config_reg()
250 *bit = g->oe_bit; in msm_config_reg()
275 const struct msm_pingroup *g; in msm_config_group_get() local
284 g = &pctrl->soc->groups[group]; in msm_config_group_get()
286 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_get()
290 val = msm_readl_ctl(pctrl, g); in msm_config_group_get()
335 val = msm_readl_io(pctrl, g); in msm_config_group_get()
336 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
358 const struct msm_pingroup *g; in msm_config_group_set() local
369 g = &pctrl->soc->groups[group]; in msm_config_group_set()
375 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_set()
412 val = msm_readl_io(pctrl, g); in msm_config_group_set()
414 val |= BIT(g->out_bit); in msm_config_group_set()
416 val &= ~BIT(g->out_bit); in msm_config_group_set()
417 msm_writel_io(val, pctrl, g); in msm_config_group_set()
440 val = msm_readl_ctl(pctrl, g); in msm_config_group_set()
443 msm_writel_ctl(val, pctrl, g); in msm_config_group_set()
458 const struct msm_pingroup *g; in msm_gpio_direction_input() local
463 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
467 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_input()
468 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
469 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_input()
478 const struct msm_pingroup *g; in msm_gpio_direction_output() local
483 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
487 val = msm_readl_io(pctrl, g); in msm_gpio_direction_output()
489 val |= BIT(g->out_bit); in msm_gpio_direction_output()
491 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
492 msm_writel_io(val, pctrl, g); in msm_gpio_direction_output()
494 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_output()
495 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
496 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_output()
506 const struct msm_pingroup *g; in msm_gpio_get_direction() local
509 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
511 val = msm_readl_ctl(pctrl, g); in msm_gpio_get_direction()
513 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT : in msm_gpio_get_direction()
519 const struct msm_pingroup *g; in msm_gpio_get() local
523 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
525 val = msm_readl_io(pctrl, g); in msm_gpio_get()
526 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
531 const struct msm_pingroup *g; in msm_gpio_set() local
536 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
540 val = msm_readl_io(pctrl, g); in msm_gpio_set()
542 val |= BIT(g->out_bit); in msm_gpio_set()
544 val &= ~BIT(g->out_bit); in msm_gpio_set()
545 msm_writel_io(val, pctrl, g); in msm_gpio_set()
559 const struct msm_pingroup *g; in msm_gpio_dbg_show_one() local
584 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
585 ctl_reg = msm_readl_ctl(pctrl, g); in msm_gpio_dbg_show_one()
586 io_reg = msm_readl_io(pctrl, g); in msm_gpio_dbg_show_one()
588 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
589 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
590 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
591 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
594 val = !!(io_reg & BIT(g->out_bit)); in msm_gpio_dbg_show_one()
596 val = !!(io_reg & BIT(g->in_bit)); in msm_gpio_dbg_show_one()
598 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in"); in msm_gpio_dbg_show_one()
704 const struct msm_pingroup *g, in msm_gpio_update_dual_edge_pos() argument
712 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
714 pol = msm_readl_intr_cfg(pctrl, g); in msm_gpio_update_dual_edge_pos()
715 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
716 msm_writel_intr_cfg(pol, pctrl, g); in msm_gpio_update_dual_edge_pos()
718 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
719 intstat = msm_readl_intr_status(pctrl, g); in msm_gpio_update_dual_edge_pos()
731 const struct msm_pingroup *g; in msm_gpio_irq_mask() local
741 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
745 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_mask()
767 val &= ~BIT(g->intr_raw_status_bit); in msm_gpio_irq_mask()
769 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
770 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_mask()
781 const struct msm_pingroup *g; in msm_gpio_irq_clear_unmask() local
791 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_clear_unmask()
801 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_clear_unmask()
802 val &= ~BIT(g->intr_status_bit); in msm_gpio_irq_clear_unmask()
803 msm_writel_intr_status(val, pctrl, g); in msm_gpio_irq_clear_unmask()
806 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_clear_unmask()
807 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_clear_unmask()
808 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_clear_unmask()
809 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_clear_unmask()
858 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent() local
864 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
877 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
895 const struct msm_pingroup *g; in msm_gpio_irq_ack() local
905 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
909 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_ack()
910 if (g->intr_ack_high) in msm_gpio_irq_ack()
911 val |= BIT(g->intr_status_bit); in msm_gpio_irq_ack()
913 val &= ~BIT(g->intr_status_bit); in msm_gpio_irq_ack()
914 msm_writel_intr_status(val, pctrl, g); in msm_gpio_irq_ack()
917 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_ack()
937 const struct msm_pingroup *g; in msm_gpio_irq_set_type() local
957 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
964 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
974 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
979 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
980 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
988 val = msm_readl_intr_target(pctrl, g); in msm_gpio_irq_set_type()
989 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
990 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
991 msm_writel_intr_target(val, pctrl, g); in msm_gpio_irq_set_type()
999 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_set_type()
1000 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1001 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
1002 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1003 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1006 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1007 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1010 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1011 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1014 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1015 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1020 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1023 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
1024 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1025 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1028 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1029 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1032 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1035 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1036 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1041 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1047 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_set_type()
1050 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_set_type()
1153 const struct msm_pingroup *g; in msm_gpio_irq_handler() local
1168 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1169 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_handler()
1170 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()