1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/pinctrl/pinconf-generic.h>
169 	INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit),
170 	INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit),
171 	INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data),
172 	INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow),
173 	INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data),
174 	INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit),
175 	INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit),
176 	INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit),
177 	INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft),
178 	{ "lcd-no-pins", },
179 	INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1),
180 	INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2),
181 	INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3),
182 	INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4),
183 	INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe),
194 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
195 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
196 static const char *jz4740_uart1_groups[] = { "uart1-data", };
198 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins",
201 	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
213 	{ "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
296 	INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit),
297 	INGENIC_PIN_GROUP("mmc0-4bit", jz4725b_mmc0_4bit),
298 	INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit),
299 	INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit),
300 	INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data),
301 	INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1),
302 	INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2),
303 	INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3),
304 	INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4),
305 	INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale),
306 	INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe),
313 	INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit),
314 	INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit),
315 	INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit),
316 	INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit),
317 	INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special),
318 	INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic),
321 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
322 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
323 static const char *jz4725b_uart_groups[] = { "uart-data", };
325 	"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
326 	"nand-cle-ale", "nand-fre-fwe",
335 	"lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
336 	"lcd-special", "lcd-generic",
489 	INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data),
490 	INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow),
491 	INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data),
492 	INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow),
493 	INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data),
494 	INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow),
495 	INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data),
496 	INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow),
497 	INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a),
498 	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a),
499 	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e),
500 	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e),
501 	INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e),
502 	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d),
503 	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d),
504 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e),
505 	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e),
506 	INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e),
507 	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b),
508 	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b),
509 	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e),
510 	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e),
511 	INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e),
512 	INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data),
513 	INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data),
514 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale),
515 	INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr),
516 	INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we),
517 	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe),
518 	INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait),
519 	INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1),
520 	INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2),
521 	INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3),
522 	INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4),
523 	INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5),
524 	INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6),
525 	INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0),
526 	INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1),
527 	INGENIC_PIN_GROUP("cim-data", jz4760_cim),
528 	INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit),
529 	{ "lcd-no-pins", },
540 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
541 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
542 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
543 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
545 	"mmc0-1bit-a", "mmc0-4bit-a",
546 	"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
549 	"mmc1-1bit-d", "mmc1-4bit-d",
550 	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
553 	"mmc2-1bit-b", "mmc2-4bit-b",
554 	"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
557 	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
558 	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
560 static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
561 static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
562 static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
563 static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
564 static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
565 static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
566 static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
567 static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
568 static const char *jz4760_cim_groups[] = { "cim-data", };
569 static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
588 	{ "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
589 	{ "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
590 	{ "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
591 	{ "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
592 	{ "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
593 	{ "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
838 	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
839 	INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
840 	INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
841 	INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
842 	INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data),
843 	INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow),
844 	INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
845 	INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
846 	INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a),
847 	INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b),
848 	INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d),
849 	INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e),
850 	INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a),
851 	INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b),
852 	INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d),
853 	INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e),
854 	INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a),
855 	INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b),
856 	INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d),
857 	INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e),
858 	INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b),
859 	INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d),
860 	INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e),
861 	INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a),
862 	INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b),
863 	INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d),
864 	INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e),
865 	INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b),
866 	INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d),
867 	INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e),
868 	INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b),
869 	INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d),
870 	INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e),
871 	INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b),
872 	INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d),
873 	INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e),
874 	INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b),
875 	INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d),
876 	INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e),
877 	INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b),
878 	INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d),
879 	INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e),
880 	INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b),
881 	INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d),
882 	INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e),
883 	INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b),
884 	INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d),
885 	INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e),
886 	INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
887 	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
888 	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
889 	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
890 	INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e),
891 	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
892 	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
893 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
894 	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
895 	INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e),
896 	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
897 	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
898 	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
899 	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
900 	INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e),
901 	INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data),
902 	INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data),
903 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
904 	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
905 	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
906 	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
907 	INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
908 	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
909 	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
910 	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
911 	INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
912 	INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
913 	INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
914 	INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
915 	INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
916 	INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
917 	INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit),
918 	INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit),
919 	INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
920 	{ "lcd-no-pins", },
929 	INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii),
930 	INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii),
931 	INGENIC_PIN_GROUP("otg-vbus", jz4770_otg),
934 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
935 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
936 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
937 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
939 	"ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
940 	"ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
941 	"ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
942 	"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
943 	"ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
944 	"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
947 	"ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
948 	"ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
949 	"ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
950 	"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
951 	"ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
952 	"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
955 	"mmc0-1bit-a", "mmc0-4bit-a",
956 	"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
959 	"mmc1-1bit-d", "mmc1-4bit-d",
960 	"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
963 	"mmc2-1bit-b", "mmc2-4bit-b",
964 	"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
967 	"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
968 	"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
970 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
971 static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
972 static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
973 static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
974 static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
975 static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
976 static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
977 static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
978 static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
979 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
980 static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
989 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
990 static const char *jz4770_otg_groups[] = { "otg-vbus", };
1003 	{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1004 	{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1005 	{ "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1006 	{ "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1007 	{ "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1008 	{ "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1141 	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
1142 	INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
1143 	INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
1144 	INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
1145 	INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data),
1146 	INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow),
1147 	INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
1148 	INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
1149 	INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data),
1150 	INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19),
1151 	INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21),
1152 	INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28),
1153 	INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b),
1154 	INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d),
1155 	INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e),
1156 	INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20),
1157 	INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27),
1158 	INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b),
1159 	INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d),
1160 	INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e),
1161 	INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a),
1162 	INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5),
1163 	INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28),
1164 	INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d),
1165 	INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e),
1166 	INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b),
1167 	INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d),
1168 	INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e),
1169 	INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23),
1170 	INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25),
1171 	INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b),
1172 	INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d),
1173 	INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e),
1174 	INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b),
1175 	INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d),
1176 	INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e),
1177 	INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b),
1178 	INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d),
1179 	INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e),
1180 	INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b),
1181 	INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d),
1182 	INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e),
1183 	INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b),
1184 	INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d),
1185 	INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e),
1186 	INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b),
1187 	INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d),
1188 	INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e),
1189 	INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b),
1190 	INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d),
1191 	INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e),
1192 	INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b),
1193 	INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d),
1194 	INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e),
1195 	INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
1196 	INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
1197 	INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a),
1198 	INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
1199 	INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
1200 	INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
1201 	INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
1202 	INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
1203 	INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
1204 	INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
1205 	INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
1206 	INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
1207 	INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
1208 	INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data),
1209 	INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
1210 	INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
1211 	INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
1212 	INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
1213 	INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
1214 	INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
1215 	INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
1216 	INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
1217 	INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
1218 	INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
1219 	INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
1220 	INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
1221 	INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
1222 	INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
1223 	INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3),
1224 	INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e),
1225 	INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f),
1226 	INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx),
1227 	INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx),
1228 	INGENIC_PIN_GROUP("i2s-clk-txrx", jz4780_i2s_clk_txrx),
1229 	INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx),
1230 	INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk),
1231 	INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc),
1232 	INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit),
1233 	INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
1234 	{ "lcd-no-pins", },
1245 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1246 static const char *jz4780_uart4_groups[] = { "uart4-data", };
1248 	"ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1249 	"ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1250 	"ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",
1251 	"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1252 	"ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1253 	"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1256 	"ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1257 	"ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1258 	"ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1259 	"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1260 	"ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1261 	"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1264 	"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1265 	"mmc0-1bit-e", "mmc0-4bit-e",
1268 	"mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
1271 	"mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
1274 	"nemc-data", "nemc-cle-ale", "nemc-addr",
1275 	"nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1277 static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
1278 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
1280 	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1282 static const char *jz4780_cim_groups[] = { "cim-data", };
1283 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
1297 	{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1298 	{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1299 	{ "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1300 	{ "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1301 	{ "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1302 	{ "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1319 	{ "hdmi-ddc", jz4780_hdmi_ddc_groups,
1473 	INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data),
1474 	INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow),
1475 	INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a),
1476 	INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d),
1477 	INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow),
1478 	INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a),
1479 	INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d),
1481 	INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22),
1482 	INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29),
1483 	INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d),
1484 	INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23),
1485 	INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28),
1486 	INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d),
1487 	INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24),
1488 	INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26),
1489 	INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d),
1490 	INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20),
1491 	INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31),
1492 	INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25),
1493 	INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27),
1494 	INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d),
1495 	INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21),
1496 	INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30),
1497 	INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit),
1498 	INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit),
1499 	INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit),
1500 	INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit),
1501 	INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit),
1502 	INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data),
1503 	INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data),
1504 	INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr),
1505 	INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we),
1506 	INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait),
1507 	INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1),
1508 	INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2),
1509 	INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0),
1510 	INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a),
1511 	INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c),
1512 	INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2),
1513 	INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx),
1514 	INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx),
1515 	INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx),
1516 	INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk),
1517 	INGENIC_PIN_GROUP("cim-data", x1000_cim),
1518 	INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit),
1519 	INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit),
1520 	{ "lcd-no-pins", },
1529 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1531 	"uart1-data-a", "uart1-data-d", "uart1-hwflow",
1533 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
1536 	"ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
1537 	"ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
1538 	"ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
1539 	"ssi-gpc-a-20", "ssi-gpc-a-31",
1540 	"ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
1541 	"ssi-ce1-a-21", "ssi-ce1-a-30",
1544 	"mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
1547 	"mmc1-1bit", "mmc1-4bit",
1550 	"emc-8bit-data", "emc-16bit-data",
1551 	"emc-addr", "emc-rd-we", "emc-wait",
1553 static const char *x1000_cs1_groups[] = { "emc-cs1", };
1554 static const char *x1000_cs2_groups[] = { "emc-cs2", };
1555 static const char *x1000_i2c0_groups[] = { "i2c0-data", };
1556 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
1557 static const char *x1000_i2c2_groups[] = { "i2c2-data", };
1559 	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1561 static const char *x1000_cim_groups[] = { "cim-data", };
1563 	"lcd-8bit", "lcd-16bit", "lcd-no-pins",
1581 	{ "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
1582 	{ "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
1661 	INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data),
1662 	INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow),
1663 	INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a),
1664 	INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d),
1665 	INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow),
1666 	INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a),
1667 	INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d),
1669 	INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit),
1670 	INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit),
1671 	INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0),
1672 	INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a),
1673 	INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c),
1674 	INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2),
1675 	INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx),
1676 	INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx),
1677 	INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx),
1678 	INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk),
1679 	INGENIC_PIN_GROUP("cim-data", x1500_cim),
1680 	{ "lcd-no-pins", },
1688 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1690 	"uart1-data-a", "uart1-data-d", "uart1-hwflow",
1692 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
1693 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
1694 static const char *x1500_i2c0_groups[] = { "i2c0-data", };
1695 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
1696 static const char *x1500_i2c2_groups[] = { "i2c2-data", };
1698 	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1700 static const char *x1500_cim_groups[] = { "cim-data", };
1701 static const char *x1500_lcd_groups[] = { "lcd-no-pins", };
1713 	{ "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), },
1877 	INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data),
1878 	INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow),
1879 	INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data),
1881 	INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt),
1882 	INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr),
1883 	INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk),
1884 	INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc),
1885 	INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0),
1886 	INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1),
1887 	INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c),
1888 	INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c),
1889 	INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c),
1890 	INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c),
1891 	INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c),
1892 	INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c),
1893 	INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d),
1894 	INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d),
1895 	INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d),
1896 	INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d),
1897 	INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d),
1898 	INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d),
1899 	INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit),
1900 	INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit),
1901 	INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit),
1902 	INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit),
1903 	INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0),
1904 	INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1),
1905 	INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2),
1906 	INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx),
1907 	INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx),
1908 	INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx),
1909 	INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx),
1910 	INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk),
1911 	INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit),
1912 	INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit),
1913 	INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit),
1914 	{ "lcd-no-pins", },
1915 	INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b),
1916 	INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c),
1917 	INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b),
1918 	INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c),
1919 	INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8),
1920 	INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13),
1921 	INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9),
1922 	INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14),
1923 	INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15),
1924 	INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25),
1925 	INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16),
1926 	INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26),
1927 	INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17),
1928 	INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27),
1929 	INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18),
1930 	INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28),
1934 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1935 static const char *x1830_uart1_groups[] = { "uart1-data", };
1938 	"ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
1941 	"ssi1-dt-c", "ssi1-dt-d",
1942 	"ssi1-dr-c", "ssi1-dr-d",
1943 	"ssi1-clk-c", "ssi1-clk-d",
1944 	"ssi1-gpc-c", "ssi1-gpc-d",
1945 	"ssi1-ce0-c", "ssi1-ce0-d",
1946 	"ssi1-ce1-c", "ssi1-ce1-d",
1948 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
1949 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
1950 static const char *x1830_i2c0_groups[] = { "i2c0-data", };
1951 static const char *x1830_i2c1_groups[] = { "i2c1-data", };
1952 static const char *x1830_i2c2_groups[] = { "i2c2-data", };
1954 	"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1957 	"lcd-rgb-18bit", "lcd-slcd-8bit", "lcd-slcd-16bit", "lcd-no-pins",
1959 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
1960 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
1961 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
1962 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
1963 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
1964 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
1965 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
1966 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
2009 	regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);  in ingenic_gpio_read_reg()
2022 	regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));  in ingenic_gpio_set_bit()
2033 	regmap_write(jzgc->jzpc->map, REG_PZ_BASE(  in ingenic_gpio_shadow_set_bit()
2034 			jzgc->jzpc->info->reg_offset) + reg, BIT(offset));  in ingenic_gpio_shadow_set_bit()
2039 	regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(  in ingenic_gpio_shadow_set_bit_load()
2040 			jzgc->jzpc->info->reg_offset),  in ingenic_gpio_shadow_set_bit_load()
2041 			jzgc->gc.base / PINS_PER_GPIO_CHIP);  in ingenic_gpio_shadow_set_bit_load()
2055 	if (jzgc->jzpc->info->version >= ID_JZ4760)  in ingenic_gpio_set_value()
2085 	if (jzgc->jzpc->info->version >= ID_JZ4760) {  in irq_set_type()
2093 	if (jzgc->jzpc->info->version >= ID_X1000) {  in irq_set_type()
2108 	ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);  in ingenic_gpio_irq_mask()
2116 	ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);  in ingenic_gpio_irq_unmask()
2123 	int irq = irqd->hwirq;  in ingenic_gpio_irq_enable()
2125 	if (jzgc->jzpc->info->version >= ID_JZ4760)  in ingenic_gpio_irq_enable()
2137 	int irq = irqd->hwirq;  in ingenic_gpio_irq_disable()
2141 	if (jzgc->jzpc->info->version >= ID_JZ4760)  in ingenic_gpio_irq_disable()
2151 	int irq = irqd->hwirq;  in ingenic_gpio_irq_ack()
2166 	if (jzgc->jzpc->info->version >= ID_JZ4760)  in ingenic_gpio_irq_ack()
2194 		 * best we can do is to set up a single-edge interrupt and then  in ingenic_gpio_irq_set_type()
2197 		bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq);  in ingenic_gpio_irq_set_type()
2202 	irq_set_type(jzgc, irqd->hwirq, type);  in ingenic_gpio_irq_set_type()
2211 	return irq_set_irq_wake(jzgc->irq, on);  in ingenic_gpio_irq_set_wake()
2218 	struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);  in ingenic_gpio_irq_handler()
2223 	if (jzgc->jzpc->info->version >= ID_JZ4760)  in ingenic_gpio_irq_handler()
2229 		generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));  in ingenic_gpio_irq_handler()
2251 	return pinctrl_gpio_direction_input(gc->base + offset);  in ingenic_gpio_direction_input()
2258 	return pinctrl_gpio_direction_output(gc->base + offset);  in ingenic_gpio_direction_output()
2267 	regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_config_pin()
2276 	regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +  in ingenic_shadow_config_pin()
2283 	regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),  in ingenic_shadow_config_pin_load()
2294 	regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);  in ingenic_get_pin_config()
2302 	struct ingenic_pinctrl *jzpc = jzgc->jzpc;  in ingenic_gpio_get_direction()
2303 	unsigned int pin = gc->base + offset;  in ingenic_gpio_get_direction()
2305 	if (jzpc->info->version >= ID_JZ4760) {  in ingenic_gpio_get_direction()
2334 	ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq);  in ingenic_gpio_irq_request()
2338 	return gpiochip_reqres_irq(gpio_chip, data->hwirq);  in ingenic_gpio_irq_request()
2345 	return gpiochip_relres_irq(gpio_chip, data->hwirq);  in ingenic_gpio_irq_release()
2354 	dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",  in ingenic_pinmux_set_pin_fn()
2357 	if (jzpc->info->version >= ID_X1000) {  in ingenic_pinmux_set_pin_fn()
2363 	} else if (jzpc->info->version >= ID_JZ4760) {  in ingenic_pinmux_set_pin_fn()
2387 		return -EINVAL;  in ingenic_pinmux_set_mux()
2391 		return -EINVAL;  in ingenic_pinmux_set_mux()
2393 	dev_dbg(pctldev->dev, "enable function %s group %s\n",  in ingenic_pinmux_set_mux()
2394 		func->name, grp->name);  in ingenic_pinmux_set_mux()
2396 	for (i = 0; i < grp->num_pins; i++) {  in ingenic_pinmux_set_mux()
2397 		int *pin_modes = grp->data;  in ingenic_pinmux_set_mux()
2399 		ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);  in ingenic_pinmux_set_mux()
2413 	dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",  in ingenic_pinmux_gpio_set_direction()
2416 	if (jzpc->info->version >= ID_X1000) {  in ingenic_pinmux_gpio_set_direction()
2421 	} else if (jzpc->info->version >= ID_JZ4760) {  in ingenic_pinmux_gpio_set_direction()
2451 	if (jzpc->info->version >= ID_JZ4760)  in ingenic_pinconf_get()
2459 			return -EINVAL;  in ingenic_pinconf_get()
2463 		if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx)))  in ingenic_pinconf_get()
2464 			return -EINVAL;  in ingenic_pinconf_get()
2468 		if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx)))  in ingenic_pinconf_get()
2469 			return -EINVAL;  in ingenic_pinconf_get()
2473 		return -ENOTSUPP;  in ingenic_pinconf_get()
2483 	if (jzpc->info->version >= ID_X1830) {  in ingenic_set_bias()
2490 			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_set_bias()
2492 			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_set_bias()
2495 			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_set_bias()
2497 			regmap_write(jzpc->map, offt * jzpc->info->reg_offset +  in ingenic_set_bias()
2501 	} else if (jzpc->info->version >= ID_JZ4760) {  in ingenic_set_bias()
2511 	if (jzpc->info->version >= ID_JZ4760)  in ingenic_set_output_level()
2534 			return -ENOTSUPP;  in ingenic_pinconf_set()
2543 			dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",  in ingenic_pinconf_set()
2549 			if (!(jzpc->info->pull_ups[offt] & BIT(idx)))  in ingenic_pinconf_set()
2550 				return -EINVAL;  in ingenic_pinconf_set()
2551 			dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",  in ingenic_pinconf_set()
2557 			if (!(jzpc->info->pull_downs[offt] & BIT(idx)))  in ingenic_pinconf_set()
2558 				return -EINVAL;  in ingenic_pinconf_set()
2559 			dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",  in ingenic_pinconf_set()
2594 			return -ENOTSUPP;  in ingenic_pinconf_group_get()
2598 			return -ENOTSUPP;  in ingenic_pinconf_group_get()
2643 	{ .compatible = "ingenic,jz4740-gpio", },
2644 	{ .compatible = "ingenic,jz4725b-gpio", },
2645 	{ .compatible = "ingenic,jz4760-gpio", },
2646 	{ .compatible = "ingenic,jz4770-gpio", },
2647 	{ .compatible = "ingenic,jz4780-gpio", },
2648 	{ .compatible = "ingenic,x1000-gpio", },
2649 	{ .compatible = "ingenic,x1830-gpio", },
2657 	struct device *dev = jzpc->dev;  in ingenic_gpio_probe()
2670 		return -ENOMEM;  in ingenic_gpio_probe()
2672 	jzgc->jzpc = jzpc;  in ingenic_gpio_probe()
2673 	jzgc->reg_base = bank * jzpc->info->reg_offset;  in ingenic_gpio_probe()
2675 	jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);  in ingenic_gpio_probe()
2676 	if (!jzgc->gc.label)  in ingenic_gpio_probe()
2677 		return -ENOMEM;  in ingenic_gpio_probe()
2683 	jzgc->gc.base = bank * 32;  in ingenic_gpio_probe()
2685 	jzgc->gc.ngpio = 32;  in ingenic_gpio_probe()
2686 	jzgc->gc.parent = dev;  in ingenic_gpio_probe()
2687 	jzgc->gc.of_node = node;  in ingenic_gpio_probe()
2688 	jzgc->gc.owner = THIS_MODULE;  in ingenic_gpio_probe()
2690 	jzgc->gc.set = ingenic_gpio_set;  in ingenic_gpio_probe()
2691 	jzgc->gc.get = ingenic_gpio_get;  in ingenic_gpio_probe()
2692 	jzgc->gc.direction_input = ingenic_gpio_direction_input;  in ingenic_gpio_probe()
2693 	jzgc->gc.direction_output = ingenic_gpio_direction_output;  in ingenic_gpio_probe()
2694 	jzgc->gc.get_direction = ingenic_gpio_get_direction;  in ingenic_gpio_probe()
2695 	jzgc->gc.request = gpiochip_generic_request;  in ingenic_gpio_probe()
2696 	jzgc->gc.free = gpiochip_generic_free;  in ingenic_gpio_probe()
2698 	jzgc->irq = irq_of_parse_and_map(node, 0);  in ingenic_gpio_probe()
2699 	if (!jzgc->irq)  in ingenic_gpio_probe()
2700 		return -EINVAL;  in ingenic_gpio_probe()
2702 	jzgc->irq_chip.name = jzgc->gc.label;  in ingenic_gpio_probe()
2703 	jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable;  in ingenic_gpio_probe()
2704 	jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable;  in ingenic_gpio_probe()
2705 	jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask;  in ingenic_gpio_probe()
2706 	jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask;  in ingenic_gpio_probe()
2707 	jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack;  in ingenic_gpio_probe()
2708 	jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type;  in ingenic_gpio_probe()
2709 	jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;  in ingenic_gpio_probe()
2710 	jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request;  in ingenic_gpio_probe()
2711 	jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release;  in ingenic_gpio_probe()
2712 	jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;  in ingenic_gpio_probe()
2714 	girq = &jzgc->gc.irq;  in ingenic_gpio_probe()
2715 	girq->chip = &jzgc->irq_chip;  in ingenic_gpio_probe()
2716 	girq->parent_handler = ingenic_gpio_irq_handler;  in ingenic_gpio_probe()
2717 	girq->num_parents = 1;  in ingenic_gpio_probe()
2718 	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),  in ingenic_gpio_probe()
2720 	if (!girq->parents)  in ingenic_gpio_probe()
2721 		return -ENOMEM;  in ingenic_gpio_probe()
2722 	girq->parents[0] = jzgc->irq;  in ingenic_gpio_probe()
2723 	girq->default_type = IRQ_TYPE_NONE;  in ingenic_gpio_probe()
2724 	girq->handler = handle_level_irq;  in ingenic_gpio_probe()
2726 	err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);  in ingenic_gpio_probe()
2735 	struct device *dev = &pdev->dev;  in ingenic_pinctrl_probe()
2746 		return -ENOMEM;  in ingenic_pinctrl_probe()
2752 	jzpc->map = devm_regmap_init_mmio(dev, base,  in ingenic_pinctrl_probe()
2754 	if (IS_ERR(jzpc->map)) {  in ingenic_pinctrl_probe()
2756 		return PTR_ERR(jzpc->map);  in ingenic_pinctrl_probe()
2759 	jzpc->dev = dev;  in ingenic_pinctrl_probe()
2760 	jzpc->info = chip_info = of_device_get_match_data(dev);  in ingenic_pinctrl_probe()
2762 	pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);  in ingenic_pinctrl_probe()
2764 		return -ENOMEM;  in ingenic_pinctrl_probe()
2767 	pctl_desc->name = dev_name(dev);  in ingenic_pinctrl_probe()
2768 	pctl_desc->owner = THIS_MODULE;  in ingenic_pinctrl_probe()
2769 	pctl_desc->pctlops = &ingenic_pctlops;  in ingenic_pinctrl_probe()
2770 	pctl_desc->pmxops = &ingenic_pmxops;  in ingenic_pinctrl_probe()
2771 	pctl_desc->confops = &ingenic_confops;  in ingenic_pinctrl_probe()
2772 	pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;  in ingenic_pinctrl_probe()
2773 	pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,  in ingenic_pinctrl_probe()
2774 			pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);  in ingenic_pinctrl_probe()
2775 	if (!jzpc->pdesc)  in ingenic_pinctrl_probe()
2776 		return -ENOMEM;  in ingenic_pinctrl_probe()
2778 	for (i = 0; i < pctl_desc->npins; i++) {  in ingenic_pinctrl_probe()
2779 		jzpc->pdesc[i].number = i;  in ingenic_pinctrl_probe()
2780 		jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",  in ingenic_pinctrl_probe()
2785 	jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);  in ingenic_pinctrl_probe()
2786 	if (IS_ERR(jzpc->pctl)) {  in ingenic_pinctrl_probe()
2788 		return PTR_ERR(jzpc->pctl);  in ingenic_pinctrl_probe()
2791 	for (i = 0; i < chip_info->num_groups; i++) {  in ingenic_pinctrl_probe()
2792 		const struct group_desc *group = &chip_info->groups[i];  in ingenic_pinctrl_probe()
2794 		err = pinctrl_generic_add_group(jzpc->pctl, group->name,  in ingenic_pinctrl_probe()
2795 				group->pins, group->num_pins, group->data);  in ingenic_pinctrl_probe()
2798 					group->name);  in ingenic_pinctrl_probe()
2803 	for (i = 0; i < chip_info->num_functions; i++) {  in ingenic_pinctrl_probe()
2804 		const struct function_desc *func = &chip_info->functions[i];  in ingenic_pinctrl_probe()
2806 		err = pinmux_generic_add_function(jzpc->pctl, func->name,  in ingenic_pinctrl_probe()
2807 				func->group_names, func->num_group_names,  in ingenic_pinctrl_probe()
2808 				func->data);  in ingenic_pinctrl_probe()
2811 					func->name);  in ingenic_pinctrl_probe()
2816 	dev_set_drvdata(dev, jzpc->map);  in ingenic_pinctrl_probe()
2818 	for_each_child_of_node(dev->of_node, node) {  in ingenic_pinctrl_probe()
2830 	{ .compatible = "ingenic,jz4740-pinctrl", .data = &jz4740_chip_info },
2831 	{ .compatible = "ingenic,jz4725b-pinctrl", .data = &jz4725b_chip_info },
2832 	{ .compatible = "ingenic,jz4760-pinctrl", .data = &jz4760_chip_info },
2833 	{ .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760_chip_info },
2834 	{ .compatible = "ingenic,jz4770-pinctrl", .data = &jz4770_chip_info },
2835 	{ .compatible = "ingenic,jz4780-pinctrl", .data = &jz4780_chip_info },
2836 	{ .compatible = "ingenic,x1000-pinctrl", .data = &x1000_chip_info },
2837 	{ .compatible = "ingenic,x1000e-pinctrl", .data = &x1000_chip_info },
2838 	{ .compatible = "ingenic,x1500-pinctrl", .data = &x1500_chip_info },
2839 	{ .compatible = "ingenic,x1830-pinctrl", .data = &x1830_chip_info },
2845 		.name = "pinctrl-ingenic",