Lines Matching +full:serial +full:- +full:pins
6 * This is a group-only pin controller.
17 #include <linux/pinctrl/pinconf-generic.h>
22 #include "pinctrl-utils.h"
24 #define DRIVER_NAME "pinctrl-gemini"
27 * struct gemini_pin_conf - information about configuring a pin
39 * struct gemini_pmx - state holder for the gemini pin controller
45 * @flash_pin: whether the flash pin (extended pins for parallel
62 * struct gemini_pin_group - describes a Gemini pin group
64 * @pins: an array of discrete physical pins used in this group, taken
65 * from the driver-local pin enumeration space
66 * @num_pins: the number of pins in this group array, i.e. the number of
67 * elements in .pins so we can iterate over that array
76 const unsigned int *pins; member
83 /* Some straight-forward control registers */
96 * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot
99 * - For the bits named *_DISABLE, once you enable something, it cannot be
129 "serial flash",
532 /* GMII, ethernet pins */
576 267, /* UART_SIN serial input, RX */
577 322, /* UART_SOUT serial output, TX */
604 /* NAND flash pins */
610 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
618 * The parallel flash can be set up in a 26-bit address bus mode exposing
619 * A[0-15] (A[15] takes the place of ALE), but it has the
620 * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
627 /* The extra pins */
632 /* Serial flash pins CE0, CE1, DI, DO, CK */
638 /* The GPIO0B (1-4) pins overlap with TVC and ICE */
641 /* The GPIO0C (5-7) pins overlap with ICE */
644 /* The GPIO0D (9,10) pins overlap with UART RX/TX */
647 /* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */
650 /* The GPIO0F (16) pins overlap with LCD */
653 /* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */
656 /* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */
659 /* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */
662 /* The GPIO0J (23) pins overlap with all flash */
665 /* The GPIO0K (24,25) pins overlap with all flash and LCD */
668 /* The GPIO0L (26-29) pins overlap with parallel flash */
671 /* The GPIO0M (30,31) pins overlap with parallel flash and NAND flash */
674 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
677 /* The GPIO1B (5-10, 27) pins overlap with just IDE */
682 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
688 /* The GPIO1D (28-31) pins overlap with LCD and TVC */
691 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
694 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
697 /* The GPIO2C (8-31) pins overlap with PCI */
707 .pins = gnd_3512_pins,
712 .pins = dram_3512_pins,
718 .pins = rtc_3512_pins,
723 .pins = power_3512_pins,
728 .pins = system_3512_pins,
733 .pins = vcontrol_3512_pins,
738 .pins = ice_3512_pins,
744 .pins = ide_3512_pins,
753 .pins = sata_3512_pins,
758 .pins = usb_3512_pins,
763 .pins = gmii_gmac0_3512_pins,
769 .pins = gmii_gmac1_3512_pins,
771 /* Bring out RGMII on the GMAC1 pins */
777 .pins = pci_3512_pins,
785 .pins = lpc_3512_pins,
787 /* Conflict with SSP and UART modem pins */
793 .pins = lcd_3512_pins,
801 .pins = ssp_3512_pins,
803 /* Conflict with LPC and UART modem pins */
809 .pins = uart_rxtx_3512_pins,
815 .pins = uart_modem_3512_pins,
825 .pins = tvc_3512_pins,
833 .pins = tvc_clk_3512_pins,
838 * The construction is done such that it is possible to use a serial
840 * possible to use NAND and parallel flash together. To use serial
846 .pins = nflash_3512_pins,
848 /* Conflict with IDE, parallel and serial flash */
854 .pins = pflash_3512_pins,
856 /* Conflict with IDE, NAND and serial flash */
862 .pins = sflash_3512_pins,
870 .pins = gpio0a_3512_pins,
877 .pins = gpio0b_3512_pins,
884 .pins = gpio0c_3512_pins,
890 .pins = gpio0d_3512_pins,
896 .pins = gpio0e_3512_pins,
898 /* Conflict with LPC, UART modem pins, SSP */
903 .pins = gpio0f_3512_pins,
910 .pins = gpio0g_3512_pins,
917 .pins = gpio0h_3512_pins,
924 .pins = gpio0i_3512_pins,
926 /* Conflict with serial flash */
931 .pins = gpio0j_3512_pins,
939 .pins = gpio0k_3512_pins,
948 .pins = gpio0l_3512_pins,
955 .pins = gpio0m_3512_pins,
962 .pins = gpio1a_3512_pins,
970 .pins = gpio1b_3512_pins,
977 .pins = gpio1c_3512_pins,
985 .pins = gpio1d_3512_pins,
992 .pins = gpio2a_3512_pins,
999 .pins = gpio2b_3512_pins,
1006 .pins = gpio2c_3512_pins,
1481 /* GMII, ethernet pins */
1525 313, /* UART_SIN serial input, RX */
1526 335, /* UART_SOUT serial output, TX */
1553 /* NAND flash pins */
1559 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
1567 * The parallel flash can be set up in a 26-bit address bus mode exposing
1568 * A[0-15] (A[15] takes the place of ALE), but it has the
1569 * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
1576 /* The extra pins */
1581 /* Serial flash pins CE0, CE1, DI, DO, CK */
1584 /* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */
1587 /* The GPIO0B (5-7) pins overlap with ICE */
1590 /* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */
1593 /* The GPIO0D (9,10) pins overlap with UART RX/TX */
1596 /* The GPIO0E (16) pins overlap with LCD */
1599 /* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */
1602 /* The GPIO0G (19,20,26-29) pins overlap with parallel flash */
1605 /* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */
1608 /* The GPIO0I (23) pins overlap with all flash */
1611 /* The GPIO0J (24,25) pins overlap with all flash and LCD */
1614 /* The GPIO0K (30,31) pins overlap with NAND flash */
1617 /* The GPIO0L (0) pins overlap with TVC_CLK */
1620 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
1623 /* The GPIO1B (5-10,27) pins overlap with just IDE */
1626 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
1632 /* The GPIO1D (28-31) pins overlap with TVC */
1635 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
1638 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
1641 /* The GPIO2C (8-31) pins overlap with PCI */
1651 .pins = gnd_3516_pins,
1656 .pins = dram_3516_pins,
1662 .pins = rtc_3516_pins,
1667 .pins = power_3516_pins,
1672 .pins = cir_3516_pins,
1677 .pins = system_3516_pins,
1682 .pins = vcontrol_3516_pins,
1687 .pins = ice_3516_pins,
1693 .pins = ide_3516_pins,
1702 .pins = sata_3516_pins,
1707 .pins = usb_3516_pins,
1712 .pins = gmii_gmac0_3516_pins,
1719 .pins = gmii_gmac1_3516_pins,
1721 /* Bring out RGMII on the GMAC1 pins */
1728 .pins = pci_3516_pins,
1736 .pins = lpc_3516_pins,
1744 .pins = lcd_3516_pins,
1751 .pins = ssp_3516_pins,
1759 .pins = uart_rxtx_3516_pins,
1765 .pins = uart_modem_3516_pins,
1775 .pins = tvc_3516_pins,
1783 .pins = tvc_clk_3516_pins,
1788 * The construction is done such that it is possible to use a serial
1790 * possible to use NAND and parallel flash together. To use serial
1796 .pins = nflash_3516_pins,
1798 /* Conflict with IDE, parallel and serial flash */
1804 .pins = pflash_3516_pins,
1806 /* Conflict with IDE, NAND and serial flash */
1812 .pins = sflash_3516_pins,
1820 .pins = gpio0a_3516_pins,
1827 .pins = gpio0b_3516_pins,
1833 .pins = gpio0c_3516_pins,
1840 .pins = gpio0d_3516_pins,
1846 .pins = gpio0e_3516_pins,
1853 .pins = gpio0f_3516_pins,
1860 .pins = gpio0g_3516_pins,
1867 .pins = gpio0h_3516_pins,
1869 /* Conflict with serial flash */
1874 .pins = gpio0i_3516_pins,
1882 .pins = gpio0j_3516_pins,
1891 .pins = gpio0k_3516_pins,
1898 .pins = gpio0l_3516_pins,
1905 .pins = gpio1a_3516_pins,
1913 .pins = gpio1b_3516_pins,
1920 .pins = gpio1c_3516_pins,
1928 .pins = gpio1d_3516_pins,
1935 .pins = gpio2a_3516_pins,
1942 .pins = gpio2b_3516_pins,
1949 .pins = gpio2c_3516_pins,
1960 if (pmx->is_3512) in gemini_get_groups_count()
1962 if (pmx->is_3516) in gemini_get_groups_count()
1972 if (pmx->is_3512) in gemini_get_group_name()
1974 if (pmx->is_3516) in gemini_get_group_name()
1981 const unsigned int **pins, in gemini_get_group_pins() argument
1987 if (pmx->flash_pin && in gemini_get_group_pins()
1988 pmx->is_3512 && in gemini_get_group_pins()
1990 *pins = pflash_3512_pins_extended; in gemini_get_group_pins()
1994 if (pmx->flash_pin && in gemini_get_group_pins()
1995 pmx->is_3516 && in gemini_get_group_pins()
1997 *pins = pflash_3516_pins_extended; in gemini_get_group_pins()
2001 if (pmx->is_3512) { in gemini_get_group_pins()
2002 *pins = gemini_3512_pin_groups[selector].pins; in gemini_get_group_pins()
2005 if (pmx->is_3516) { in gemini_get_group_pins()
2006 *pins = gemini_3516_pin_groups[selector].pins; in gemini_get_group_pins()
2028 * struct gemini_pmx_func - describes Gemini pinmux functions
2201 if (pmx->is_3512) in gemini_pmx_set_mux()
2203 else if (pmx->is_3516) in gemini_pmx_set_mux()
2206 dev_err(pmx->dev, "invalid SoC type\n"); in gemini_pmx_set_mux()
2207 return -ENODEV; in gemini_pmx_set_mux()
2210 dev_dbg(pmx->dev, in gemini_pmx_set_mux()
2212 func->name, grp->name); in gemini_pmx_set_mux()
2214 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before); in gemini_pmx_set_mux()
2215 regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL, in gemini_pmx_set_mux()
2216 grp->mask | grp->value, in gemini_pmx_set_mux()
2217 grp->value); in gemini_pmx_set_mux()
2218 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after); in gemini_pmx_set_mux()
2223 expected = before &= ~grp->mask; in gemini_pmx_set_mux()
2224 expected |= grp->value; in gemini_pmx_set_mux()
2228 tmp = grp->mask; in gemini_pmx_set_mux()
2234 dev_err(pmx->dev, in gemini_pmx_set_mux()
2239 dev_err(pmx->dev, in gemini_pmx_set_mux()
2243 dev_dbg(pmx->dev, in gemini_pmx_set_mux()
2250 tmp = grp->value; in gemini_pmx_set_mux()
2256 dev_err(pmx->dev, in gemini_pmx_set_mux()
2261 dev_err(pmx->dev, in gemini_pmx_set_mux()
2265 dev_dbg(pmx->dev, in gemini_pmx_set_mux()
2369 for (i = 0; i < pmx->nconfs; i++) { in gemini_get_pin_conf()
2370 retconf = &pmx->confs[i]; in gemini_get_pin_conf()
2371 if (retconf->pin == pin) in gemini_get_pin_conf()
2389 return -ENOTSUPP; in gemini_pinconf_get()
2390 regmap_read(pmx->map, conf->reg, &val); in gemini_pinconf_get()
2391 val &= conf->mask; in gemini_pinconf_get()
2392 val >>= (ffs(conf->mask) - 1); in gemini_pinconf_get()
2396 return -ENOTSUPP; in gemini_pinconf_get()
2419 return -EINVAL; in gemini_pinconf_set()
2422 dev_err(pmx->dev, in gemini_pinconf_set()
2424 return -ENOTSUPP; in gemini_pinconf_set()
2426 arg <<= (ffs(conf->mask) - 1); in gemini_pinconf_set()
2427 dev_dbg(pmx->dev, in gemini_pinconf_set()
2429 pin, conf->mask, arg); in gemini_pinconf_set()
2430 regmap_update_bits(pmx->map, conf->reg, conf->mask, arg); in gemini_pinconf_set()
2433 dev_err(pmx->dev, "Invalid config param %04x\n", param); in gemini_pinconf_set()
2434 return -ENOTSUPP; in gemini_pinconf_set()
2453 if (pmx->is_3512) in gemini_pinconf_group_set()
2455 if (pmx->is_3516) in gemini_pinconf_group_set()
2459 if (!grp->driving_mask) { in gemini_pinconf_group_set()
2460 dev_err(pmx->dev, "pin config group \"%s\" does " in gemini_pinconf_group_set()
2462 grp->name); in gemini_pinconf_group_set()
2463 return -EINVAL; in gemini_pinconf_group_set()
2486 dev_err(pmx->dev, in gemini_pinconf_group_set()
2489 return -ENOTSUPP; in gemini_pinconf_group_set()
2491 val <<= (ffs(grp->driving_mask) - 1); in gemini_pinconf_group_set()
2492 regmap_update_bits(pmx->map, GLOBAL_IODRIVE, in gemini_pinconf_group_set()
2493 grp->driving_mask, in gemini_pinconf_group_set()
2495 dev_dbg(pmx->dev, in gemini_pinconf_group_set()
2497 grp->name, arg, grp->driving_mask, val); in gemini_pinconf_group_set()
2500 dev_err(pmx->dev, "invalid config param %04x\n", param); in gemini_pinconf_group_set()
2501 return -ENOTSUPP; in gemini_pinconf_group_set()
2527 struct device *dev = &pdev->dev; in gemini_pmx_probe()
2535 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); in gemini_pmx_probe()
2537 return -ENOMEM; in gemini_pmx_probe()
2539 pmx->dev = &pdev->dev; in gemini_pmx_probe()
2540 parent = dev->parent; in gemini_pmx_probe()
2543 return -ENODEV; in gemini_pmx_probe()
2545 map = syscon_node_to_regmap(parent->of_node); in gemini_pmx_probe()
2550 pmx->map = map; in gemini_pmx_probe()
2561 pmx->is_3512 = true; in gemini_pmx_probe()
2562 pmx->confs = gemini_confs_3512; in gemini_pmx_probe()
2563 pmx->nconfs = ARRAY_SIZE(gemini_confs_3512); in gemini_pmx_probe()
2564 gemini_pmx_desc.pins = gemini_3512_pins; in gemini_pmx_probe()
2568 pmx->is_3516 = true; in gemini_pmx_probe()
2569 pmx->confs = gemini_confs_3516; in gemini_pmx_probe()
2570 pmx->nconfs = ARRAY_SIZE(gemini_confs_3516); in gemini_pmx_probe()
2571 gemini_pmx_desc.pins = gemini_3516_pins; in gemini_pmx_probe()
2576 return -ENODEV; in gemini_pmx_probe()
2594 pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN); in gemini_pmx_probe()
2595 dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set"); in gemini_pmx_probe()
2597 pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx); in gemini_pmx_probe()
2598 if (IS_ERR(pmx->pctl)) { in gemini_pmx_probe()
2600 return PTR_ERR(pmx->pctl); in gemini_pmx_probe()
2609 { .compatible = "cortina,gemini-pinctrl" },