1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/pinctrl/pinconf-generic.h>
21 #include "../pinctrl-utils.h"
22 #include "pinctrl-aspeed.h"
32  * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
35  * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
37  * reset control and MAC clock configuration registers. The AST2500 goes a step
45 #define SCU80           0x80 /* Multi-function Pin Control #1 */
46 #define SCU84           0x84 /* Multi-function Pin Control #2 */
47 #define SCU88           0x88 /* Multi-function Pin Control #3 */
48 #define SCU8C           0x8C /* Multi-function Pin Control #4 */
49 #define SCU90           0x90 /* Multi-function Pin Control #5 */
50 #define SCU94           0x94 /* Multi-function Pin Control #6 */
51 #define SCUA0           0xA0 /* Multi-function Pin Control #7 */
52 #define SCUA4           0xA4 /* Multi-function Pin Control #8 */
53 #define SCUA8           0xA8 /* Multi-function Pin Control #9 */
54 #define SCUAC           0xAC /* Multi-function Pin Control #10 */
62 /* LHCR0 is offset from the end of the H8S/2168-compatible registers */
1540 /* CRT DVO disabled, configured for single-edge mode */
1543 /* CRT DVO disabled, configured for dual-edge mode */
1546 /* CRT DVO enabled, configured for single-edge mode */
1549 /* CRT DVO enabled, configured for dual-edge mode */
2544 	/* GPIOs T[0-5] (RGMII1 Tx pins) */
2550 	/* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
2556 	/* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
2560 	/* GPIOs V[2-7] (RGMII2 Rx pins) */
2564 	/* ADC pull-downs (SCUA8[19:4]) */
2601 	 * banks D and E is handled by the GPIO driver - GPIO passthrough is
2602 	 * treated like any other non-GPIO mux function. There is a catch
2605 	 * fully support pass-through debounce.
2621 		WARN(!ctx->maps[ip], "Missing SCU syscon!");  in aspeed_g5_acquire_regmap()
2622 		return ctx->maps[ip];  in aspeed_g5_acquire_regmap()
2626 		return ERR_PTR(-EINVAL);  in aspeed_g5_acquire_regmap()
2628 	if (likely(ctx->maps[ip]))  in aspeed_g5_acquire_regmap()
2629 		return ctx->maps[ip];  in aspeed_g5_acquire_regmap()
2635 		node = of_parse_phandle(ctx->dev->of_node,  in aspeed_g5_acquire_regmap()
2636 					"aspeed,external-nodes", 0);  in aspeed_g5_acquire_regmap()
2643 			return ERR_PTR(-ENODEV);  in aspeed_g5_acquire_regmap()
2645 		ctx->maps[ASPEED_IP_GFX] = map;  in aspeed_g5_acquire_regmap()
2646 		dev_dbg(ctx->dev, "Acquired GFX regmap");  in aspeed_g5_acquire_regmap()
2654 		node = of_parse_phandle(ctx->dev->of_node,  in aspeed_g5_acquire_regmap()
2655 					"aspeed,external-nodes", 1);  in aspeed_g5_acquire_regmap()
2657 			map = syscon_node_to_regmap(node->parent);  in aspeed_g5_acquire_regmap()
2662 			return ERR_PTR(-ENODEV);  in aspeed_g5_acquire_regmap()
2664 		ctx->maps[ASPEED_IP_LPC] = map;  in aspeed_g5_acquire_regmap()
2665 		dev_dbg(ctx->dev, "Acquired LPC regmap");  in aspeed_g5_acquire_regmap()
2669 	return ERR_PTR(-EINVAL);  in aspeed_g5_acquire_regmap()
2679 	for (i = 0; i < expr->ndescs; i++) {  in aspeed_g5_sig_expr_eval()
2680 		const struct aspeed_sig_desc *desc = &expr->descs[i];  in aspeed_g5_sig_expr_eval()
2683 		map = aspeed_g5_acquire_regmap(ctx, desc->ip);  in aspeed_g5_sig_expr_eval()
2685 			dev_err(ctx->dev,  in aspeed_g5_sig_expr_eval()
2687 				desc->ip);  in aspeed_g5_sig_expr_eval()
2691 		ret = aspeed_sig_desc_eval(desc, enabled, ctx->maps[desc->ip]);  in aspeed_g5_sig_expr_eval()
2719 	for (i = 0; i < expr->ndescs; i++) {  in aspeed_g5_sig_expr_set()
2720 		const struct aspeed_sig_desc *desc = &expr->descs[i];  in aspeed_g5_sig_expr_set()
2721 		u32 pattern = enable ? desc->enable : desc->disable;  in aspeed_g5_sig_expr_set()
2722 		u32 val = (pattern << __ffs(desc->mask));  in aspeed_g5_sig_expr_set()
2725 		map = aspeed_g5_acquire_regmap(ctx, desc->ip);  in aspeed_g5_sig_expr_set()
2727 			dev_err(ctx->dev,  in aspeed_g5_sig_expr_set()
2729 				desc->ip);  in aspeed_g5_sig_expr_set()
2734 		 * Strap registers are configured in hardware or by early-boot  in aspeed_g5_sig_expr_set()
2735 		 * firmware. Treat them as read-only despite that we can write  in aspeed_g5_sig_expr_set()
2737 		 * deconfigured and is the reason we re-evaluate after writing  in aspeed_g5_sig_expr_set()
2741 		 * as those are commonly used with front-panel buttons to allow  in aspeed_g5_sig_expr_set()
2744 		 * must be disabled for the BMC to control host power-on and  in aspeed_g5_sig_expr_set()
2747 		if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&  in aspeed_g5_sig_expr_set()
2748 		    !(desc->mask & (BIT(21) | BIT(22))))  in aspeed_g5_sig_expr_set()
2751 		if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)  in aspeed_g5_sig_expr_set()
2754 		/* On AST2500, Set bits in SCU70 are cleared from SCU7C */  in aspeed_g5_sig_expr_set()
2755 		if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) {  in aspeed_g5_sig_expr_set()
2756 			u32 value = ~val & desc->mask;  in aspeed_g5_sig_expr_set()
2759 				ret = regmap_write(ctx->maps[desc->ip],  in aspeed_g5_sig_expr_set()
2766 		ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,  in aspeed_g5_sig_expr_set()
2767 					 desc->mask, val);  in aspeed_g5_sig_expr_set()
2778 		return -EPERM;  in aspeed_g5_sig_expr_set()
2785 	{ PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
2786 	{ PIN_CONFIG_BIAS_DISABLE,   -1, 1, BIT_MASK(0)},
2839 	.name = "aspeed-g5-pinctrl",
2854 	aspeed_g5_pinctrl_data.pinmux.dev = &pdev->dev;  in aspeed_g5_pinctrl_probe()
2861 	{ .compatible = "aspeed,ast2500-pinctrl", },
2863 	 * The aspeed,g5-pinctrl compatible has been removed the from the
2866 	{ .compatible = "aspeed,g5-pinctrl", },
2873 		.name = "aspeed-g5-pinctrl",