Lines Matching +full:g4 +full:- +full:pinctrl
1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/pinctrl/pinctrl.h>
13 #include <linux/pinctrl/pinmux.h>
14 #include <linux/pinctrl/pinconf.h>
15 #include <linux/pinctrl/pinconf-generic.h>
20 #include "../pinctrl-utils.h"
21 #include "pinmux-aspeed.h"
22 #include "pinctrl-aspeed.h"
32 * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
35 * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
44 #define SCU80 0x80 /* Multi-function Pin Control #1 */
45 #define SCU84 0x84 /* Multi-function Pin Control #2 */
46 #define SCU88 0x88 /* Multi-function Pin Control #3 */
47 #define SCU8C 0x8C /* Multi-function Pin Control #4 */
48 #define SCU90 0x90 /* Multi-function Pin Control #5 */
49 #define SCU94 0x94 /* Multi-function Pin Control #6 */
50 #define SCUA0 0xA0 /* Multi-function Pin Control #7 */
51 #define SCUA4 0xA4 /* Multi-function Pin Control #8 */
52 #define SCUA8 0xA8 /* Multi-function Pin Control #9 */
53 #define SCUAC 0xAC /* Multi-function Pin Control #10 */
1092 * it is only mentioned in one location. Particularly, the Multi-function Pins
1900 /* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216
1901 * pins becomes 220. Four additional non-GPIO-capable pins are present for USB.
2473 /* GPIOs T[0-5] (RGMII1 Tx pins) */
2478 /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
2483 /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
2487 /* GPIOs V[2-7] (RGMII2 Rx pins) */
2491 /* ADC pull-downs (SCUA8[19:4]) */
2527 * SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for
2528 * banks D and E is handled by the GPIO driver - GPIO passthrough is
2529 * treated like any other non-GPIO mux function. There is a catch
2531 * controller. Due to this tangle between GPIO and pinctrl we don't yet
2532 * fully support pass-through debounce.
2551 for (i = 0; i < expr->ndescs; i++) { in aspeed_g4_sig_expr_set()
2552 const struct aspeed_sig_desc *desc = &expr->descs[i]; in aspeed_g4_sig_expr_set()
2553 u32 pattern = enable ? desc->enable : desc->disable; in aspeed_g4_sig_expr_set()
2554 u32 val = (pattern << __ffs(desc->mask)); in aspeed_g4_sig_expr_set()
2556 if (!ctx->maps[desc->ip]) in aspeed_g4_sig_expr_set()
2557 return -ENODEV; in aspeed_g4_sig_expr_set()
2560 * Strap registers are configured in hardware or by early-boot in aspeed_g4_sig_expr_set()
2561 * firmware. Treat them as read-only despite that we can write in aspeed_g4_sig_expr_set()
2563 * deconfigured and is the reason we re-evaluate after writing in aspeed_g4_sig_expr_set()
2567 * as those are commonly used with front-panel buttons to allow in aspeed_g4_sig_expr_set()
2570 * must be disabled for the BMC to control host power-on and in aspeed_g4_sig_expr_set()
2573 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 && in aspeed_g4_sig_expr_set()
2574 !(desc->mask & (BIT(21) | BIT(22)))) in aspeed_g4_sig_expr_set()
2577 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2) in aspeed_g4_sig_expr_set()
2580 ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg, in aspeed_g4_sig_expr_set()
2581 desc->mask, val); in aspeed_g4_sig_expr_set()
2592 return -EPERM; in aspeed_g4_sig_expr_set()
2599 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
2600 { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
2652 .name = "aspeed-g4-pinctrl",
2672 { .compatible = "aspeed,ast2400-pinctrl", },
2674 * The aspeed,g4-pinctrl compatible has been removed the from the
2677 { .compatible = "aspeed,g4-pinctrl", },
2684 .name = "aspeed-g4-pinctrl",