Lines Matching full:lane
29 * Lane Registers
151 #define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
152 #define XPSGTR_TYPE_SATA_1 3 /* SATA controller lane 1 */
153 #define XPSGTR_TYPE_PCIE_0 4 /* PCIe controller lane 0 */
154 #define XPSGTR_TYPE_PCIE_1 5 /* PCIe controller lane 1 */
155 #define XPSGTR_TYPE_PCIE_2 6 /* PCIe controller lane 2 */
156 #define XPSGTR_TYPE_PCIE_3 7 /* PCIe controller lane 3 */
157 #define XPSGTR_TYPE_DP_0 8 /* Display Port controller lane 0 */
158 #define XPSGTR_TYPE_DP_1 9 /* Display Port controller lane 1 */
170 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
184 * struct xpsgtr_phy - representation of a lane
186 * @type: controller which uses this lane
187 * @lane: lane number
188 * @protocol: protocol in which the lane operates
196 u8 lane; member
275 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_read_phy()
284 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_write_phy()
293 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_clr_set_phy()
330 "lane %u (type %u, protocol %u): PLL lock timeout\n", in xpsgtr_wait_pll_lock()
331 gtr_phy->lane, gtr_phy->type, gtr_phy->protocol); in xpsgtr_wait_pll_lock()
345 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
348 /* Enable lane clock sharing, if required */ in xpsgtr_configure_pll()
349 if (gtr_phy->refclk != gtr_phy->lane) { in xpsgtr_configure_pll()
351 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
385 /* Configure the lane protocol. */
391 switch (gtr_phy->lane) { in xpsgtr_lane_set_protocol()
407 /* We already checked 0 <= lane <= 3 */ in xpsgtr_lane_set_protocol()
439 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET); in xpsgtr_phy_init_sata()
449 PROT_BUS_WIDTH_10 << (gtr_phy->lane * PROT_BUS_WIDTH_SHIFT)); in xpsgtr_phy_init_sgmii()
451 PROT_BUS_WIDTH_10 << (gtr_phy->lane * PROT_BUS_WIDTH_SHIFT)); in xpsgtr_phy_init_sgmii()
488 * shutdown during suspend or when gt lane is changed from current one) in xpsgtr_phy_init_required()
518 * we need to configure any lane ICM_CFG to valid protocol. This in xpsgtr_phy_tx_term_fix()
588 * Configure the PLL, the lane protocol, and perform protocol-specific in xpsgtr_phy_init()
630 * lane 0 last. in xpsgtr_phy_power_on()
663 /* Set the lane type and protocol based on the PHY type and instance number. */
774 * Get the PHY parameters from the OF arguments and derive the lane in xpsgtr_xlate()
779 dev_err(dev, "Invalid lane number %u\n", phy_lane); in xpsgtr_xlate()
803 * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type in xpsgtr_xlate()
804 * is allowed to operate on the lane. in xpsgtr_xlate()
951 gtr_phy->lane = port; in xpsgtr_probe()