201 struct wiz {  struct
228 static int wiz_reset(struct wiz *wiz)  in wiz_reset()  argument
232 	ret = regmap_field_write(wiz->por_en, 0x1);  in wiz_reset()
238 	ret = regmap_field_write(wiz->por_en, 0x0);  in wiz_reset()
245 static int wiz_mode_select(struct wiz *wiz)  in wiz_mode_select()  argument
247 	u32 num_lanes = wiz->num_lanes;  in wiz_mode_select()
253 		if (wiz->lane_phy_type[i] == PHY_TYPE_DP)  in wiz_mode_select()
258 		ret = regmap_field_write(wiz->p_standard_mode[i], mode);  in wiz_mode_select()
266 static int wiz_init_raw_interface(struct wiz *wiz, bool enable)  in wiz_init_raw_interface()  argument
268 	u32 num_lanes = wiz->num_lanes;  in wiz_init_raw_interface()
273 		ret = regmap_field_write(wiz->p_align[i], enable);  in wiz_init_raw_interface()
277 		ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);  in wiz_init_raw_interface()
285 static int wiz_init(struct wiz *wiz)  in wiz_init()  argument
287 	struct device *dev = wiz->dev;  in wiz_init()
290 	ret = wiz_reset(wiz);  in wiz_init()
292 		dev_err(dev, "WIZ reset failed\n");  in wiz_init()
296 	ret = wiz_mode_select(wiz);  in wiz_init()
298 		dev_err(dev, "WIZ mode select failed\n");  in wiz_init()
302 	ret = wiz_init_raw_interface(wiz, true);  in wiz_init()
304 		dev_err(dev, "WIZ interface initialization failed\n");  in wiz_init()
311 static int wiz_regfield_init(struct wiz *wiz)  in wiz_regfield_init()  argument
315 	struct regmap *regmap = wiz->regmap;  in wiz_regfield_init()
316 	int num_lanes = wiz->num_lanes;  in wiz_regfield_init()
317 	struct device *dev = wiz->dev;  in wiz_regfield_init()
320 	wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);  in wiz_regfield_init()
321 	if (IS_ERR(wiz->por_en)) {  in wiz_regfield_init()
323 		return PTR_ERR(wiz->por_en);  in wiz_regfield_init()
326 	wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
328 	if (IS_ERR(wiz->phy_reset_n)) {  in wiz_regfield_init()
330 		return PTR_ERR(wiz->phy_reset_n);  in wiz_regfield_init()
333 	wiz->pma_cmn_refclk_int_mode =  in wiz_regfield_init()
335 	if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {  in wiz_regfield_init()
337 		return PTR_ERR(wiz->pma_cmn_refclk_int_mode);  in wiz_regfield_init()
340 	wiz->pma_cmn_refclk_mode =  in wiz_regfield_init()
342 	if (IS_ERR(wiz->pma_cmn_refclk_mode)) {  in wiz_regfield_init()
344 		return PTR_ERR(wiz->pma_cmn_refclk_mode);  in wiz_regfield_init()
347 	clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK_DIG_DIV];  in wiz_regfield_init()
355 	if (wiz->type == J721E_WIZ_16G) {  in wiz_regfield_init()
356 		clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK1_DIG_DIV];  in wiz_regfield_init()
366 	clk_mux_sel = &wiz->clk_mux_sel[PLL0_REFCLK];  in wiz_regfield_init()
374 	clk_mux_sel = &wiz->clk_mux_sel[PLL1_REFCLK];  in wiz_regfield_init()
382 	clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG];  in wiz_regfield_init()
383 	if (wiz->type == J721E_WIZ_10G)  in wiz_regfield_init()
398 		wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
400 		if (IS_ERR(wiz->p_enable[i])) {  in wiz_regfield_init()
402 			return PTR_ERR(wiz->p_enable[i]);  in wiz_regfield_init()
405 		wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
407 		if (IS_ERR(wiz->p_align[i])) {  in wiz_regfield_init()
409 			return PTR_ERR(wiz->p_align[i]);  in wiz_regfield_init()
412 		wiz->p_raw_auto_start[i] =  in wiz_regfield_init()
414 		if (IS_ERR(wiz->p_raw_auto_start[i])) {  in wiz_regfield_init()
417 			return PTR_ERR(wiz->p_raw_auto_start[i]);  in wiz_regfield_init()
420 		wiz->p_standard_mode[i] =  in wiz_regfield_init()
422 		if (IS_ERR(wiz->p_standard_mode[i])) {  in wiz_regfield_init()
425 			return PTR_ERR(wiz->p_standard_mode[i]);  in wiz_regfield_init()
429 	wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
431 	if (IS_ERR(wiz->typec_ln10_swap)) {  in wiz_regfield_init()
433 		return PTR_ERR(wiz->typec_ln10_swap);  in wiz_regfield_init()
464 static int wiz_mux_clk_register(struct wiz *wiz, struct device_node *node,  in wiz_mux_clk_register()  argument
467 	struct device *dev = wiz->dev;  in wiz_mux_clk_register()
559 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,  in wiz_div_clk_register()  argument
563 	struct device *dev = wiz->dev;  in wiz_div_clk_register()
607 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)  in wiz_clock_cleanup()  argument
609 	struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;  in wiz_clock_cleanup()
620 static int wiz_clock_init(struct wiz *wiz, struct device_node *node)  in wiz_clock_init()  argument
622 	struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;  in wiz_clock_init()
623 	struct device *dev = wiz->dev;  in wiz_clock_init()
640 		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);  in wiz_clock_init()
642 		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);  in wiz_clock_init()
653 		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);  in wiz_clock_init()
655 		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);  in wiz_clock_init()
666 		ret = wiz_mux_clk_register(wiz, clk_node, clk_mux_sel[i].field,  in wiz_clock_init()
678 	for (i = 0; i < wiz->clk_div_sel_num; i++) {  in wiz_clock_init()
687 		ret = wiz_div_clk_register(wiz, clk_node, clk_div_sel[i].field,  in wiz_clock_init()
701 	wiz_clock_cleanup(wiz, node);  in wiz_clock_init()
710 	struct wiz *wiz = dev_get_drvdata(dev);  in wiz_phy_reset_assert()  local
714 		ret = regmap_field_write(wiz->phy_reset_n, false);  in wiz_phy_reset_assert()
718 	ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);  in wiz_phy_reset_assert()
726 	struct wiz *wiz = dev_get_drvdata(dev);  in wiz_phy_reset_deassert()  local
730 	if (id == 0 && wiz->gpio_typec_dir) {  in wiz_phy_reset_deassert()
731 		if (wiz->typec_dir_delay)  in wiz_phy_reset_deassert()
732 			msleep_interruptible(wiz->typec_dir_delay);  in wiz_phy_reset_deassert()
734 		if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))  in wiz_phy_reset_deassert()
735 			regmap_field_write(wiz->typec_ln10_swap, 1);  in wiz_phy_reset_deassert()
737 			regmap_field_write(wiz->typec_ln10_swap, 0);  in wiz_phy_reset_deassert()
741 		ret = regmap_field_write(wiz->phy_reset_n, true);  in wiz_phy_reset_deassert()
745 	if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)  in wiz_phy_reset_deassert()
746 		ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);  in wiz_phy_reset_deassert()
748 		ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);  in wiz_phy_reset_deassert()
767 		.compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G
770 		.compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G
776 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)  in wiz_get_lane_phy_types()  argument
804 			wiz->lane_phy_type[i] = phy_type;  in wiz_get_lane_phy_types()
820 	struct wiz *wiz;  in wiz_probe()  local
824 	wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);  in wiz_probe()
825 	if (!wiz)  in wiz_probe()
828 	wiz->type = (enum wiz_type)of_device_get_match_data(dev);  in wiz_probe()
867 	wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",  in wiz_probe()
869 	if (IS_ERR(wiz->gpio_typec_dir)) {  in wiz_probe()
870 		ret = PTR_ERR(wiz->gpio_typec_dir);  in wiz_probe()
877 	if (wiz->gpio_typec_dir) {  in wiz_probe()
879 					   &wiz->typec_dir_delay);  in wiz_probe()
887 			wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;  in wiz_probe()
889 		if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||  in wiz_probe()
890 		    wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {  in wiz_probe()
896 	ret = wiz_get_lane_phy_types(dev, wiz);  in wiz_probe()
900 	wiz->dev = dev;  in wiz_probe()
901 	wiz->regmap = regmap;  in wiz_probe()
902 	wiz->num_lanes = num_lanes;  in wiz_probe()
903 	if (wiz->type == J721E_WIZ_10G)  in wiz_probe()
904 		wiz->clk_mux_sel = clk_mux_sel_10g;  in wiz_probe()
906 		wiz->clk_mux_sel = clk_mux_sel_16g;  in wiz_probe()
908 	wiz->clk_div_sel = clk_div_sel;  in wiz_probe()
910 	if (wiz->type == J721E_WIZ_10G)  in wiz_probe()
911 		wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;  in wiz_probe()
913 		wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;  in wiz_probe()
915 	platform_set_drvdata(pdev, wiz);  in wiz_probe()
917 	ret = wiz_regfield_init(wiz);  in wiz_probe()
923 	phy_reset_dev = &wiz->wiz_phy_reset_dev;  in wiz_probe()
944 	ret = wiz_clock_init(wiz, node);  in wiz_probe()
956 	wiz->serdes_pdev = serdes_pdev;  in wiz_probe()
958 	ret = wiz_init(wiz);  in wiz_probe()
960 		dev_err(dev, "WIZ initialization failed\n");  in wiz_probe()
971 	wiz_clock_cleanup(wiz, node);  in wiz_probe()
988 	struct wiz *wiz;  in wiz_remove()  local
990 	wiz = dev_get_drvdata(dev);  in wiz_remove()
991 	serdes_pdev = wiz->serdes_pdev;  in wiz_remove()
994 	wiz_clock_cleanup(wiz, node);  in wiz_remove()
1005 		.name	= "wiz",
1012 MODULE_DESCRIPTION("TI J721E WIZ driver");