Lines Matching +full:j721e +full:- +full:wiz +full:- +full:16 +full:g
1 // SPDX-License-Identifier: GPL-2.0
3 * Wrapper driver for SERDES used in J721E
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
11 #include <linux/clk-provider.h>
22 #include <linux/reset-controller.h>
144 .node_name = "pll0-refclk",
148 .node_name = "pll1-refclk",
152 .node_name = "refclk-dig",
163 .node_name = "pll0-refclk",
167 .node_name = "pll1-refclk",
171 .node_name = "refclk-dig",
185 .node_name = "cmn-refclk-dig-div",
189 .node_name = "cmn-refclk1-dig-div",
201 struct wiz { struct
228 static int wiz_reset(struct wiz *wiz) in wiz_reset() argument
232 ret = regmap_field_write(wiz->por_en, 0x1); in wiz_reset()
238 ret = regmap_field_write(wiz->por_en, 0x0); in wiz_reset()
245 static int wiz_mode_select(struct wiz *wiz) in wiz_mode_select() argument
247 u32 num_lanes = wiz->num_lanes; in wiz_mode_select()
253 if (wiz->lane_phy_type[i] == PHY_TYPE_DP) in wiz_mode_select()
258 ret = regmap_field_write(wiz->p_standard_mode[i], mode); in wiz_mode_select()
266 static int wiz_init_raw_interface(struct wiz *wiz, bool enable) in wiz_init_raw_interface() argument
268 u32 num_lanes = wiz->num_lanes; in wiz_init_raw_interface()
273 ret = regmap_field_write(wiz->p_align[i], enable); in wiz_init_raw_interface()
277 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); in wiz_init_raw_interface()
285 static int wiz_init(struct wiz *wiz) in wiz_init() argument
287 struct device *dev = wiz->dev; in wiz_init()
290 ret = wiz_reset(wiz); in wiz_init()
292 dev_err(dev, "WIZ reset failed\n"); in wiz_init()
296 ret = wiz_mode_select(wiz); in wiz_init()
298 dev_err(dev, "WIZ mode select failed\n"); in wiz_init()
302 ret = wiz_init_raw_interface(wiz, true); in wiz_init()
304 dev_err(dev, "WIZ interface initialization failed\n"); in wiz_init()
311 static int wiz_regfield_init(struct wiz *wiz) in wiz_regfield_init() argument
315 struct regmap *regmap = wiz->regmap; in wiz_regfield_init()
316 int num_lanes = wiz->num_lanes; in wiz_regfield_init()
317 struct device *dev = wiz->dev; in wiz_regfield_init()
320 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); in wiz_regfield_init()
321 if (IS_ERR(wiz->por_en)) { in wiz_regfield_init()
323 return PTR_ERR(wiz->por_en); in wiz_regfield_init()
326 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
328 if (IS_ERR(wiz->phy_reset_n)) { in wiz_regfield_init()
330 return PTR_ERR(wiz->phy_reset_n); in wiz_regfield_init()
333 wiz->pma_cmn_refclk_int_mode = in wiz_regfield_init()
335 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) { in wiz_regfield_init()
337 return PTR_ERR(wiz->pma_cmn_refclk_int_mode); in wiz_regfield_init()
340 wiz->pma_cmn_refclk_mode = in wiz_regfield_init()
342 if (IS_ERR(wiz->pma_cmn_refclk_mode)) { in wiz_regfield_init()
344 return PTR_ERR(wiz->pma_cmn_refclk_mode); in wiz_regfield_init()
347 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK_DIG_DIV]; in wiz_regfield_init()
348 clk_div_sel->field = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
350 if (IS_ERR(clk_div_sel->field)) { in wiz_regfield_init()
352 return PTR_ERR(clk_div_sel->field); in wiz_regfield_init()
355 if (wiz->type == J721E_WIZ_16G) { in wiz_regfield_init()
356 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK1_DIG_DIV]; in wiz_regfield_init()
357 clk_div_sel->field = in wiz_regfield_init()
360 if (IS_ERR(clk_div_sel->field)) { in wiz_regfield_init()
362 return PTR_ERR(clk_div_sel->field); in wiz_regfield_init()
366 clk_mux_sel = &wiz->clk_mux_sel[PLL0_REFCLK]; in wiz_regfield_init()
367 clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
369 if (IS_ERR(clk_mux_sel->field)) { in wiz_regfield_init()
371 return PTR_ERR(clk_mux_sel->field); in wiz_regfield_init()
374 clk_mux_sel = &wiz->clk_mux_sel[PLL1_REFCLK]; in wiz_regfield_init()
375 clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
377 if (IS_ERR(clk_mux_sel->field)) { in wiz_regfield_init()
379 return PTR_ERR(clk_mux_sel->field); in wiz_regfield_init()
382 clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG]; in wiz_regfield_init()
383 if (wiz->type == J721E_WIZ_10G) in wiz_regfield_init()
384 clk_mux_sel->field = in wiz_regfield_init()
388 clk_mux_sel->field = in wiz_regfield_init()
392 if (IS_ERR(clk_mux_sel->field)) { in wiz_regfield_init()
394 return PTR_ERR(clk_mux_sel->field); in wiz_regfield_init()
398 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
400 if (IS_ERR(wiz->p_enable[i])) { in wiz_regfield_init()
402 return PTR_ERR(wiz->p_enable[i]); in wiz_regfield_init()
405 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
407 if (IS_ERR(wiz->p_align[i])) { in wiz_regfield_init()
409 return PTR_ERR(wiz->p_align[i]); in wiz_regfield_init()
412 wiz->p_raw_auto_start[i] = in wiz_regfield_init()
414 if (IS_ERR(wiz->p_raw_auto_start[i])) { in wiz_regfield_init()
417 return PTR_ERR(wiz->p_raw_auto_start[i]); in wiz_regfield_init()
420 wiz->p_standard_mode[i] = in wiz_regfield_init()
422 if (IS_ERR(wiz->p_standard_mode[i])) { in wiz_regfield_init()
425 return PTR_ERR(wiz->p_standard_mode[i]); in wiz_regfield_init()
429 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
431 if (IS_ERR(wiz->typec_ln10_swap)) { in wiz_regfield_init()
433 return PTR_ERR(wiz->typec_ln10_swap); in wiz_regfield_init()
442 struct regmap_field *field = mux->field; in wiz_clk_mux_get_parent()
446 return clk_mux_val_to_index(hw, mux->table, 0, val); in wiz_clk_mux_get_parent()
452 struct regmap_field *field = mux->field; in wiz_clk_mux_set_parent()
455 val = mux->table[index]; in wiz_clk_mux_set_parent()
464 static int wiz_mux_clk_register(struct wiz *wiz, struct device_node *node, in wiz_mux_clk_register() argument
467 struct device *dev = wiz->dev; in wiz_mux_clk_register()
478 return -ENOMEM; in wiz_mux_clk_register()
483 return -EINVAL; in wiz_mux_clk_register()
489 return -ENOMEM; in wiz_mux_clk_register()
494 node->name); in wiz_mux_clk_register()
496 init = &mux->clk_data; in wiz_mux_clk_register()
498 init->ops = &wiz_clk_mux_ops; in wiz_mux_clk_register()
499 init->flags = CLK_SET_RATE_NO_REPARENT; in wiz_mux_clk_register()
500 init->parent_names = parent_names; in wiz_mux_clk_register()
501 init->num_parents = num_parents; in wiz_mux_clk_register()
502 init->name = clk_name; in wiz_mux_clk_register()
504 mux->field = field; in wiz_mux_clk_register()
505 mux->table = table; in wiz_mux_clk_register()
506 mux->hw.init = init; in wiz_mux_clk_register()
508 clk = devm_clk_register(dev, &mux->hw); in wiz_mux_clk_register()
523 struct regmap_field *field = div->field; in wiz_clk_div_recalc_rate()
528 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); in wiz_clk_div_recalc_rate()
536 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0); in wiz_clk_div_round_rate()
543 struct regmap_field *field = div->field; in wiz_clk_div_set_rate()
546 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); in wiz_clk_div_set_rate()
559 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node, in wiz_div_clk_register() argument
563 struct device *dev = wiz->dev; in wiz_div_clk_register()
573 return -ENOMEM; in wiz_div_clk_register()
576 node->name); in wiz_div_clk_register()
580 return -ENOMEM; in wiz_div_clk_register()
584 init = &div->clk_data; in wiz_div_clk_register()
586 init->ops = &wiz_clk_div_ops; in wiz_div_clk_register()
587 init->flags = 0; in wiz_div_clk_register()
588 init->parent_names = parent_names; in wiz_div_clk_register()
589 init->num_parents = 1; in wiz_div_clk_register()
590 init->name = clk_name; in wiz_div_clk_register()
592 div->field = field; in wiz_div_clk_register()
593 div->table = table; in wiz_div_clk_register()
594 div->hw.init = init; in wiz_div_clk_register()
596 clk = devm_clk_register(dev, &div->hw); in wiz_div_clk_register()
607 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) in wiz_clock_cleanup() argument
609 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; in wiz_clock_cleanup()
620 static int wiz_clock_init(struct wiz *wiz, struct device_node *node) in wiz_clock_init() argument
622 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; in wiz_clock_init()
623 struct device *dev = wiz->dev; in wiz_clock_init()
640 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); in wiz_clock_init()
642 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); in wiz_clock_init()
653 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); in wiz_clock_init()
655 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); in wiz_clock_init()
662 ret = -EINVAL; in wiz_clock_init()
666 ret = wiz_mux_clk_register(wiz, clk_node, clk_mux_sel[i].field, in wiz_clock_init()
678 for (i = 0; i < wiz->clk_div_sel_num; i++) { in wiz_clock_init()
683 ret = -EINVAL; in wiz_clock_init()
687 ret = wiz_div_clk_register(wiz, clk_node, clk_div_sel[i].field, in wiz_clock_init()
701 wiz_clock_cleanup(wiz, node); in wiz_clock_init()
709 struct device *dev = rcdev->dev; in wiz_phy_reset_assert()
710 struct wiz *wiz = dev_get_drvdata(dev); in wiz_phy_reset_assert() local
714 ret = regmap_field_write(wiz->phy_reset_n, false); in wiz_phy_reset_assert()
718 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE); in wiz_phy_reset_assert()
725 struct device *dev = rcdev->dev; in wiz_phy_reset_deassert()
726 struct wiz *wiz = dev_get_drvdata(dev); in wiz_phy_reset_deassert() local
729 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ in wiz_phy_reset_deassert()
730 if (id == 0 && wiz->gpio_typec_dir) { in wiz_phy_reset_deassert()
731 if (wiz->typec_dir_delay) in wiz_phy_reset_deassert()
732 msleep_interruptible(wiz->typec_dir_delay); in wiz_phy_reset_deassert()
734 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) in wiz_phy_reset_deassert()
735 regmap_field_write(wiz->typec_ln10_swap, 1); in wiz_phy_reset_deassert()
737 regmap_field_write(wiz->typec_ln10_swap, 0); in wiz_phy_reset_deassert()
741 ret = regmap_field_write(wiz->phy_reset_n, true); in wiz_phy_reset_deassert()
745 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) in wiz_phy_reset_deassert()
746 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); in wiz_phy_reset_deassert()
748 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); in wiz_phy_reset_deassert()
767 .compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G
770 .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G
776 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) in wiz_get_lane_phy_types() argument
780 serdes = of_get_child_by_name(dev->of_node, "serdes"); in wiz_get_lane_phy_types()
782 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__); in wiz_get_lane_phy_types()
783 return -EINVAL; in wiz_get_lane_phy_types()
794 __func__, subnode->name, ret); in wiz_get_lane_phy_types()
797 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes); in wiz_get_lane_phy_types()
798 of_property_read_u32(subnode, "cdns,phy-type", &phy_type); in wiz_get_lane_phy_types()
800 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, in wiz_get_lane_phy_types()
801 reg, reg + num_lanes - 1, phy_type); in wiz_get_lane_phy_types()
804 wiz->lane_phy_type[i] = phy_type; in wiz_get_lane_phy_types()
813 struct device *dev = &pdev->dev; in wiz_probe()
814 struct device_node *node = dev->of_node; in wiz_probe()
820 struct wiz *wiz; in wiz_probe() local
824 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL); in wiz_probe()
825 if (!wiz) in wiz_probe()
826 return -ENOMEM; in wiz_probe()
828 wiz->type = (enum wiz_type)of_device_get_match_data(dev); in wiz_probe()
833 return -ENODEV; in wiz_probe()
844 ret = -ENOMEM; in wiz_probe()
855 ret = of_property_read_u32(node, "num-lanes", &num_lanes); in wiz_probe()
857 dev_err(dev, "Failed to read num-lanes property\n"); in wiz_probe()
863 ret = -ENODEV; in wiz_probe()
867 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", in wiz_probe()
869 if (IS_ERR(wiz->gpio_typec_dir)) { in wiz_probe()
870 ret = PTR_ERR(wiz->gpio_typec_dir); in wiz_probe()
871 if (ret != -EPROBE_DEFER) in wiz_probe()
872 dev_err(dev, "Failed to request typec-dir gpio: %d\n", in wiz_probe()
877 if (wiz->gpio_typec_dir) { in wiz_probe()
878 ret = of_property_read_u32(node, "typec-dir-debounce-ms", in wiz_probe()
879 &wiz->typec_dir_delay); in wiz_probe()
880 if (ret && ret != -EINVAL) { in wiz_probe()
881 dev_err(dev, "Invalid typec-dir-debounce property\n"); in wiz_probe()
885 /* use min. debounce from Type-C spec if not provided in DT */ in wiz_probe()
886 if (ret == -EINVAL) in wiz_probe()
887 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN; in wiz_probe()
889 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || in wiz_probe()
890 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { in wiz_probe()
891 dev_err(dev, "Invalid typec-dir-debounce property\n"); in wiz_probe()
896 ret = wiz_get_lane_phy_types(dev, wiz); in wiz_probe()
900 wiz->dev = dev; in wiz_probe()
901 wiz->regmap = regmap; in wiz_probe()
902 wiz->num_lanes = num_lanes; in wiz_probe()
903 if (wiz->type == J721E_WIZ_10G) in wiz_probe()
904 wiz->clk_mux_sel = clk_mux_sel_10g; in wiz_probe()
906 wiz->clk_mux_sel = clk_mux_sel_16g; in wiz_probe()
908 wiz->clk_div_sel = clk_div_sel; in wiz_probe()
910 if (wiz->type == J721E_WIZ_10G) in wiz_probe()
911 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G; in wiz_probe()
913 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G; in wiz_probe()
915 platform_set_drvdata(pdev, wiz); in wiz_probe()
917 ret = wiz_regfield_init(wiz); in wiz_probe()
923 phy_reset_dev = &wiz->wiz_phy_reset_dev; in wiz_probe()
924 phy_reset_dev->dev = dev; in wiz_probe()
925 phy_reset_dev->ops = &wiz_phy_reset_ops, in wiz_probe()
926 phy_reset_dev->owner = THIS_MODULE, in wiz_probe()
927 phy_reset_dev->of_node = node; in wiz_probe()
929 phy_reset_dev->nr_resets = num_lanes + 1; in wiz_probe()
944 ret = wiz_clock_init(wiz, node); in wiz_probe()
953 ret = -ENOMEM; in wiz_probe()
956 wiz->serdes_pdev = serdes_pdev; in wiz_probe()
958 ret = wiz_init(wiz); in wiz_probe()
960 dev_err(dev, "WIZ initialization failed\n"); in wiz_probe()
968 of_platform_device_destroy(&serdes_pdev->dev, NULL); in wiz_probe()
971 wiz_clock_cleanup(wiz, node); in wiz_probe()
985 struct device *dev = &pdev->dev; in wiz_remove()
986 struct device_node *node = dev->of_node; in wiz_remove()
988 struct wiz *wiz; in wiz_remove() local
990 wiz = dev_get_drvdata(dev); in wiz_remove()
991 serdes_pdev = wiz->serdes_pdev; in wiz_remove()
993 of_platform_device_destroy(&serdes_pdev->dev, NULL); in wiz_remove()
994 wiz_clock_cleanup(wiz, node); in wiz_remove()
1005 .name = "wiz",
1012 MODULE_DESCRIPTION("TI J721E WIZ driver");