Lines Matching +full:charge +full:- +full:ctrl +full:- +full:value
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/nvmem-consumer.h>
23 #include <dt-bindings/phy/phy-qcom-qusb2.h>
105 * if yes, then offset gives index in the reg-layout
123 /* set of registers with offsets different per-PHY */
243 /* true if TUNE1 register must be updated by fused value, else TUNE2 */
287 "vdda-pll", "vdda-phy-dpdm",
292 /* struct override_param - structure holding qusb2 v2 phy overriding param
294 * to value
298 u8 value; member
301 /*struct override_params - structure holding qusb2 v2 phy overriding params
304 * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
305 * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
306 * @bias_ctrl: bias ctrl to be updated in BIAS_CONTROL_2 register
307 * @charge_ctrl: charge ctrl to be updated in CHG_CTRL2 register
321 * struct qusb2_phy - structure holding qusb2 phy attributes
333 * @cell: nvmem cell containing phy tuning value
338 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
422 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_override_phy_params()
423 struct override_params *or = &qphy->overrides; in qusb2_phy_override_phy_params()
425 if (or->imp_res_offset.override) in qusb2_phy_override_phy_params()
426 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1, in qusb2_phy_override_phy_params()
427 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
430 if (or->bias_ctrl.override) in qusb2_phy_override_phy_params()
431 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2, in qusb2_phy_override_phy_params()
432 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
435 if (or->charge_ctrl.override) in qusb2_phy_override_phy_params()
436 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2, in qusb2_phy_override_phy_params()
437 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
440 if (or->hstx_trim.override) in qusb2_phy_override_phy_params()
441 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
442 or->hstx_trim.value << HSTX_TRIM_SHIFT, in qusb2_phy_override_phy_params()
445 if (or->preemphasis.override) in qusb2_phy_override_phy_params()
446 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
447 or->preemphasis.value << PREEMPHASIS_EN_SHIFT, in qusb2_phy_override_phy_params()
450 if (or->preemphasis_width.override) { in qusb2_phy_override_phy_params()
451 if (or->preemphasis_width.value == in qusb2_phy_override_phy_params()
453 qusb2_setbits(qphy->base, in qusb2_phy_override_phy_params()
454 cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
457 qusb2_clrbits(qphy->base, in qusb2_phy_override_phy_params()
458 cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
462 if (or->hsdisc_trim.override) in qusb2_phy_override_phy_params()
463 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], in qusb2_phy_override_phy_params()
464 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT, in qusb2_phy_override_phy_params()
469 * Fetches HS Tx tuning value from nvmem and sets the
471 * For error case, skip setting the value and use the default value.
475 struct device *dev = &qphy->phy->dev; in qusb2_phy_set_tune2_param()
476 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_set_tune2_param()
480 if (!qphy->cell) in qusb2_phy_set_tune2_param()
485 * If efuse register shows value as 0x0 (indicating value is not in qusb2_phy_set_tune2_param()
487 * then use default value for high nibble that we have already in qusb2_phy_set_tune2_param()
490 val = nvmem_cell_read(qphy->cell, NULL); in qusb2_phy_set_tune2_param()
492 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); in qusb2_phy_set_tune2_param()
496 /* Fused TUNE1/2 value is the higher nibble only */ in qusb2_phy_set_tune2_param()
497 if (cfg->update_tune1_with_efuse) in qusb2_phy_set_tune2_param()
498 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_set_tune2_param()
502 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], in qusb2_phy_set_tune2_param()
512 qphy->mode = mode; in qusb2_phy_set_mode()
520 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_runtime_suspend()
523 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode); in qusb2_phy_runtime_suspend()
525 if (!qphy->phy_initialized) { in qusb2_phy_runtime_suspend()
533 * current D+/D- levels are e.g. if currently D+ high, D- low in qusb2_phy_runtime_suspend()
534 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high in qusb2_phy_runtime_suspend()
537 switch (qphy->mode) { in qusb2_phy_runtime_suspend()
555 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_suspend()
558 if (cfg->has_pll_override) { in qusb2_phy_runtime_suspend()
559 qusb2_setbits(qphy->base, in qusb2_phy_runtime_suspend()
560 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], in qusb2_phy_runtime_suspend()
565 /* enable phy auto-resume only if device is connected on bus */ in qusb2_phy_runtime_suspend()
566 if (qphy->mode != PHY_MODE_INVALID) { in qusb2_phy_runtime_suspend()
567 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], in qusb2_phy_runtime_suspend()
568 cfg->autoresume_en); in qusb2_phy_runtime_suspend()
570 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], in qusb2_phy_runtime_suspend()
571 cfg->autoresume_en); in qusb2_phy_runtime_suspend()
574 if (!qphy->has_se_clk_scheme) in qusb2_phy_runtime_suspend()
575 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_runtime_suspend()
577 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_runtime_suspend()
578 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_runtime_suspend()
586 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_runtime_resume()
589 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode); in qusb2_phy_runtime_resume()
591 if (!qphy->phy_initialized) { in qusb2_phy_runtime_resume()
596 ret = clk_prepare_enable(qphy->iface_clk); in qusb2_phy_runtime_resume()
602 ret = clk_prepare_enable(qphy->cfg_ahb_clk); in qusb2_phy_runtime_resume()
608 if (!qphy->has_se_clk_scheme) { in qusb2_phy_runtime_resume()
609 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_runtime_resume()
616 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_resume()
619 if (cfg->has_pll_override) { in qusb2_phy_runtime_resume()
620 qusb2_clrbits(qphy->base, in qusb2_phy_runtime_resume()
621 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], in qusb2_phy_runtime_resume()
628 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_runtime_resume()
630 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_runtime_resume()
638 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_init()
643 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__); in qusb2_phy_init()
646 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_init()
650 ret = clk_prepare_enable(qphy->iface_clk); in qusb2_phy_init()
652 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret); in qusb2_phy_init()
657 ret = clk_prepare_enable(qphy->cfg_ahb_clk); in qusb2_phy_init()
659 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); in qusb2_phy_init()
664 ret = reset_control_assert(qphy->phy_reset); in qusb2_phy_init()
666 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); in qusb2_phy_init()
673 ret = reset_control_deassert(qphy->phy_reset); in qusb2_phy_init()
675 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); in qusb2_phy_init()
680 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_init()
681 qphy->cfg->disable_ctrl); in qusb2_phy_init()
683 if (cfg->has_pll_test) { in qusb2_phy_init()
684 /* save reset value to override reference clock scheme later */ in qusb2_phy_init()
685 val = readl(qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
688 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, in qusb2_phy_init()
689 cfg->tbl_num); in qusb2_phy_init()
694 /* Set efuse value for tuning the PHY */ in qusb2_phy_init()
698 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_init()
704 /* Default is single-ended clock on msm8996 */ in qusb2_phy_init()
705 qphy->has_se_clk_scheme = true; in qusb2_phy_init()
707 * read TCSR_PHY_CLK_SCHEME register to check if single-ended in qusb2_phy_init()
709 * ref_clk and use single-ended clock, otherwise use differential in qusb2_phy_init()
712 if (qphy->tcsr) { in qusb2_phy_init()
713 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, in qusb2_phy_init()
716 dev_err(&phy->dev, "failed to read clk scheme reg\n"); in qusb2_phy_init()
722 dev_vdbg(&phy->dev, "%s(): select differential clk\n", in qusb2_phy_init()
724 qphy->has_se_clk_scheme = false; in qusb2_phy_init()
726 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n", in qusb2_phy_init()
731 if (!qphy->has_se_clk_scheme) { in qusb2_phy_init()
732 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_init()
734 dev_err(&phy->dev, "failed to enable ref clk, %d\n", in qusb2_phy_init()
740 if (cfg->has_pll_test) { in qusb2_phy_init()
741 if (!qphy->has_se_clk_scheme) in qusb2_phy_init()
746 writel(val, qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
749 readl(qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
755 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); in qusb2_phy_init()
756 if (!(val & cfg->mask_core_ready)) { in qusb2_phy_init()
757 dev_err(&phy->dev, in qusb2_phy_init()
759 ret = -EBUSY; in qusb2_phy_init()
762 qphy->phy_initialized = true; in qusb2_phy_init()
767 if (!qphy->has_se_clk_scheme) in qusb2_phy_init()
768 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_init()
770 reset_control_assert(qphy->phy_reset); in qusb2_phy_init()
772 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_init()
774 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_init()
776 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_init()
786 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_exit()
787 qphy->cfg->disable_ctrl); in qusb2_phy_exit()
789 if (!qphy->has_se_clk_scheme) in qusb2_phy_exit()
790 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_exit()
792 reset_control_assert(qphy->phy_reset); in qusb2_phy_exit()
794 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_exit()
795 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_exit()
797 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_exit()
799 qphy->phy_initialized = false; in qusb2_phy_exit()
813 .compatible = "qcom,ipq8074-qusb2-phy",
816 .compatible = "qcom,msm8996-qusb2-phy",
819 .compatible = "qcom,msm8998-qusb2-phy",
824 * trees that didn't include "qcom,qusb2-v2-phy"
826 .compatible = "qcom,sdm845-qusb2-phy",
829 .compatible = "qcom,qusb2-v2-phy",
843 struct device *dev = &pdev->dev; in qusb2_phy_probe()
850 u32 value; in qusb2_phy_probe() local
855 return -ENOMEM; in qusb2_phy_probe()
856 or = &qphy->overrides; in qusb2_phy_probe()
859 qphy->base = devm_ioremap_resource(dev, res); in qusb2_phy_probe()
860 if (IS_ERR(qphy->base)) in qusb2_phy_probe()
861 return PTR_ERR(qphy->base); in qusb2_phy_probe()
863 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb"); in qusb2_phy_probe()
864 if (IS_ERR(qphy->cfg_ahb_clk)) { in qusb2_phy_probe()
865 ret = PTR_ERR(qphy->cfg_ahb_clk); in qusb2_phy_probe()
866 if (ret != -EPROBE_DEFER) in qusb2_phy_probe()
871 qphy->ref_clk = devm_clk_get(dev, "ref"); in qusb2_phy_probe()
872 if (IS_ERR(qphy->ref_clk)) { in qusb2_phy_probe()
873 ret = PTR_ERR(qphy->ref_clk); in qusb2_phy_probe()
874 if (ret != -EPROBE_DEFER) in qusb2_phy_probe()
879 qphy->iface_clk = devm_clk_get_optional(dev, "iface"); in qusb2_phy_probe()
880 if (IS_ERR(qphy->iface_clk)) in qusb2_phy_probe()
881 return PTR_ERR(qphy->iface_clk); in qusb2_phy_probe()
883 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0); in qusb2_phy_probe()
884 if (IS_ERR(qphy->phy_reset)) { in qusb2_phy_probe()
886 return PTR_ERR(qphy->phy_reset); in qusb2_phy_probe()
889 num = ARRAY_SIZE(qphy->vregs); in qusb2_phy_probe()
891 qphy->vregs[i].supply = qusb2_phy_vreg_names[i]; in qusb2_phy_probe()
893 ret = devm_regulator_bulk_get(dev, num, qphy->vregs); in qusb2_phy_probe()
895 if (ret != -EPROBE_DEFER) in qusb2_phy_probe()
902 qphy->cfg = of_device_get_match_data(dev); in qusb2_phy_probe()
904 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, in qusb2_phy_probe()
905 "qcom,tcsr-syscon"); in qusb2_phy_probe()
906 if (IS_ERR(qphy->tcsr)) { in qusb2_phy_probe()
908 qphy->tcsr = NULL; in qusb2_phy_probe()
911 qphy->cell = devm_nvmem_cell_get(dev, NULL); in qusb2_phy_probe()
912 if (IS_ERR(qphy->cell)) { in qusb2_phy_probe()
913 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER) in qusb2_phy_probe()
914 return -EPROBE_DEFER; in qusb2_phy_probe()
915 qphy->cell = NULL; in qusb2_phy_probe()
916 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n"); in qusb2_phy_probe()
919 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value", in qusb2_phy_probe()
920 &value)) { in qusb2_phy_probe()
921 or->imp_res_offset.value = (u8)value; in qusb2_phy_probe()
922 or->imp_res_offset.override = true; in qusb2_phy_probe()
925 if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value", in qusb2_phy_probe()
926 &value)) { in qusb2_phy_probe()
927 or->bias_ctrl.value = (u8)value; in qusb2_phy_probe()
928 or->bias_ctrl.override = true; in qusb2_phy_probe()
931 if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value", in qusb2_phy_probe()
932 &value)) { in qusb2_phy_probe()
933 or->charge_ctrl.value = (u8)value; in qusb2_phy_probe()
934 or->charge_ctrl.override = true; in qusb2_phy_probe()
937 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value", in qusb2_phy_probe()
938 &value)) { in qusb2_phy_probe()
939 or->hstx_trim.value = (u8)value; in qusb2_phy_probe()
940 or->hstx_trim.override = true; in qusb2_phy_probe()
943 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level", in qusb2_phy_probe()
944 &value)) { in qusb2_phy_probe()
945 or->preemphasis.value = (u8)value; in qusb2_phy_probe()
946 or->preemphasis.override = true; in qusb2_phy_probe()
949 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width", in qusb2_phy_probe()
950 &value)) { in qusb2_phy_probe()
951 or->preemphasis_width.value = (u8)value; in qusb2_phy_probe()
952 or->preemphasis_width.override = true; in qusb2_phy_probe()
955 if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value", in qusb2_phy_probe()
956 &value)) { in qusb2_phy_probe()
957 or->hsdisc_trim.value = (u8)value; in qusb2_phy_probe()
958 or->hsdisc_trim.override = true; in qusb2_phy_probe()
976 qphy->phy = generic_phy; in qusb2_phy_probe()
983 dev_info(dev, "Registered Qcom-QUSB2 phy\n"); in qusb2_phy_probe()
993 .name = "qcom-qusb2-phy",