1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/phy/phy.h>
14 /* USB QSCRATCH Hardware registers */
35 /* USB QSCRATCH Hardware registers */
53 /* SSPHY control registers - Does this need 0x30? */
108 /* SS CAP register bits */
132  * @base - QCOM DWC3 PHY base virtual address.
133  * @offset - register offset.
134  * @mask - register bitmask specifying what should be updated
135  * @val - value to write.
141 	u32 write_val, tmp = readl(phy_dwc3->base + offset);  in usb_phy_write_readback()
146 	writel(write_val, phy_dwc3->base + offset);  in usb_phy_write_readback()
149 	tmp = readl(phy_dwc3->base + offset);  in usb_phy_write_readback()
153 		dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n", val, offset);  in usb_phy_write_readback()
164 		if (--retry == 0)  in wait_for_latch()
165 			return -ETIMEDOUT;  in wait_for_latch()
176  * @base - QCOM DWC3 PHY base virtual address.
177  * @addr - SSPHY address to write.
178  * @val - value to write.
185 	writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);  in usb_ss_write_phycreg()
187 	       phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);  in usb_ss_write_phycreg()
189 	ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);  in usb_ss_write_phycreg()
193 	writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);  in usb_ss_write_phycreg()
195 	       phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);  in usb_ss_write_phycreg()
197 	ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);  in usb_ss_write_phycreg()
201 	writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);  in usb_ss_write_phycreg()
203 	ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);  in usb_ss_write_phycreg()
207 		dev_err(phy_dwc3->dev, "timeout waiting for latch\n");  in usb_ss_write_phycreg()
214  * @base - QCOM DWC3 PHY base virtual address.
215  * @addr - SSPHY address to read.
222 	writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);  in usb_ss_read_phycreg()
224 	       phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);  in usb_ss_read_phycreg()
226 	ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);  in usb_ss_read_phycreg()
235 	writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);  in usb_ss_read_phycreg()
237 	ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);  in usb_ss_read_phycreg()
242 	readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);  in usb_ss_read_phycreg()
244 	writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);  in usb_ss_read_phycreg()
246 	ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);  in usb_ss_read_phycreg()
250 	*val = readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);  in usb_ss_read_phycreg()
256 static int qcom_ipq806x_usb_hs_phy_init(struct phy *phy)  in qcom_ipq806x_usb_hs_phy_init()  argument
258 	struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);  in qcom_ipq806x_usb_hs_phy_init()
262 	ret = clk_prepare_enable(phy_dwc3->xo_clk);  in qcom_ipq806x_usb_hs_phy_init()
266 	ret = clk_prepare_enable(phy_dwc3->ref_clk);  in qcom_ipq806x_usb_hs_phy_init()
268 		clk_disable_unprepare(phy_dwc3->xo_clk);  in qcom_ipq806x_usb_hs_phy_init()
274 	 * enable clamping, and disable RETENTION (power-on default is ENABLED)  in qcom_ipq806x_usb_hs_phy_init()
283 	if (!phy_dwc3->xo_clk)  in qcom_ipq806x_usb_hs_phy_init()
286 	writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);  in qcom_ipq806x_usb_hs_phy_init()
290 	writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);  in qcom_ipq806x_usb_hs_phy_init()
295 static int qcom_ipq806x_usb_hs_phy_exit(struct phy *phy)  in qcom_ipq806x_usb_hs_phy_exit()  argument
297 	struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);  in qcom_ipq806x_usb_hs_phy_exit()
299 	clk_disable_unprepare(phy_dwc3->ref_clk);  in qcom_ipq806x_usb_hs_phy_exit()
300 	clk_disable_unprepare(phy_dwc3->xo_clk);  in qcom_ipq806x_usb_hs_phy_exit()
305 static int qcom_ipq806x_usb_ss_phy_init(struct phy *phy)  in qcom_ipq806x_usb_ss_phy_init()  argument
307 	struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);  in qcom_ipq806x_usb_ss_phy_init()
311 	ret = clk_prepare_enable(phy_dwc3->xo_clk);  in qcom_ipq806x_usb_ss_phy_init()
315 	ret = clk_prepare_enable(phy_dwc3->ref_clk);  in qcom_ipq806x_usb_ss_phy_init()
317 		clk_disable_unprepare(phy_dwc3->xo_clk);  in qcom_ipq806x_usb_ss_phy_init()
321 	/* reset phy */  in qcom_ipq806x_usb_ss_phy_init()
322 	data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);  in qcom_ipq806x_usb_ss_phy_init()
324 	       phy_dwc3->base + SSUSB_PHY_CTRL_REG);  in qcom_ipq806x_usb_ss_phy_init()
326 	writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);  in qcom_ipq806x_usb_ss_phy_init()
329 	if (!phy_dwc3->xo_clk)  in qcom_ipq806x_usb_ss_phy_init()
334 	writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);  in qcom_ipq806x_usb_ss_phy_init()
340 	writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);  in qcom_ipq806x_usb_ss_phy_init()
343 	 * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates  in qcom_ipq806x_usb_ss_phy_init()
344 	 * in HS mode instead of SS mode. Workaround it by asserting  in qcom_ipq806x_usb_ss_phy_init()
380 	data |= RX_OVRD_IN_HI_RX_EQ(phy_dwc3->rx_eq);  in qcom_ipq806x_usb_ss_phy_init()
399 	data |= TX_OVRD_DRV_LO_PREEMPH(phy_dwc3->tx_deamp_3_5db);  in qcom_ipq806x_usb_ss_phy_init()
410 	data |= SSPHY_MPLL(phy_dwc3->mpll);  in qcom_ipq806x_usb_ss_phy_init()
420 	data = readl(phy_dwc3->base + SSUSB_PHY_PARAM_CTRL_1);  in qcom_ipq806x_usb_ss_phy_init()
426 		PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) |  in qcom_ipq806x_usb_ss_phy_init()
436 static int qcom_ipq806x_usb_ss_phy_exit(struct phy *phy)  in qcom_ipq806x_usb_ss_phy_exit()  argument
438 	struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);  in qcom_ipq806x_usb_ss_phy_exit()
443 	 * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention  in qcom_ipq806x_usb_ss_phy_exit()
452 	clk_disable_unprepare(phy_dwc3->ref_clk);  in qcom_ipq806x_usb_ss_phy_exit()
453 	clk_disable_unprepare(phy_dwc3->xo_clk);  in qcom_ipq806x_usb_ss_phy_exit()
477 	{ .compatible = "qcom,ipq806x-usb-phy-hs",
479 	{ .compatible = "qcom,ipq806x-usb-phy-ss",
489 	struct phy *generic_phy;  in qcom_ipq806x_usb_phy_probe()
494 	phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);  in qcom_ipq806x_usb_phy_probe()
496 		return -ENOMEM;  in qcom_ipq806x_usb_phy_probe()
498 	data = of_device_get_match_data(&pdev->dev);  in qcom_ipq806x_usb_phy_probe()
500 	phy_dwc3->dev = &pdev->dev;  in qcom_ipq806x_usb_phy_probe()
504 		return -EINVAL;  in qcom_ipq806x_usb_phy_probe()
506 	phy_dwc3->base = devm_ioremap(phy_dwc3->dev, res->start, size);  in qcom_ipq806x_usb_phy_probe()
508 	if (!phy_dwc3->base) {  in qcom_ipq806x_usb_phy_probe()
509 		dev_err(phy_dwc3->dev, "failed to map reg\n");  in qcom_ipq806x_usb_phy_probe()
510 		return -ENOMEM;  in qcom_ipq806x_usb_phy_probe()
513 	phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");  in qcom_ipq806x_usb_phy_probe()
514 	if (IS_ERR(phy_dwc3->ref_clk)) {  in qcom_ipq806x_usb_phy_probe()
515 		dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");  in qcom_ipq806x_usb_phy_probe()
516 		return PTR_ERR(phy_dwc3->ref_clk);  in qcom_ipq806x_usb_phy_probe()
519 	clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);  in qcom_ipq806x_usb_phy_probe()
521 	phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");  in qcom_ipq806x_usb_phy_probe()
522 	if (IS_ERR(phy_dwc3->xo_clk)) {  in qcom_ipq806x_usb_phy_probe()
523 		dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");  in qcom_ipq806x_usb_phy_probe()
524 		phy_dwc3->xo_clk = NULL;  in qcom_ipq806x_usb_phy_probe()
528 	if (device_property_read_u32(&pdev->dev, "qcom,rx-eq",  in qcom_ipq806x_usb_phy_probe()
529 				     &phy_dwc3->rx_eq))  in qcom_ipq806x_usb_phy_probe()
530 		phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE;  in qcom_ipq806x_usb_phy_probe()
532 	if (device_property_read_u32(&pdev->dev, "qcom,tx-deamp_3_5db",  in qcom_ipq806x_usb_phy_probe()
533 				     &phy_dwc3->tx_deamp_3_5db))  in qcom_ipq806x_usb_phy_probe()
534 		phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB;  in qcom_ipq806x_usb_phy_probe()
536 	if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))  in qcom_ipq806x_usb_phy_probe()
537 		phy_dwc3->mpll = SSPHY_MPLL_VALUE;  in qcom_ipq806x_usb_phy_probe()
539 	generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node, &data->ops);  in qcom_ipq806x_usb_phy_probe()
547 	phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,  in qcom_ipq806x_usb_phy_probe()
559 		.name	= "qcom-ipq806x-usb-phy",
566 MODULE_ALIAS("platform:phy-qcom-ipq806x-usb");
569 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
570 MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");