Lines Matching full:cmu
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
13 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
14 * operate according to the mode of operation. The first PLL CMU is only
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
27 * The Ref PLL CMU CSR (Configuration System Registers) is accessed
30 * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
33 * The Ref PLL CMU can be located within the same PHY IP or outside the PHY IP
34 * due to shared Ref PLL CMU. For PHY with Ref PLL CMU shared with another IP,
37 * to located the SDS/Ref PLL CMU module and its clock for that IP enabled.
123 /* PLL Clock Macro Unit (CMU) CSR accessing from SDS indirectly */
607 pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val); in cmu_wr()
621 pr_debug("CMU RD addr 0x%X value 0x%08X\n", reg, *data); in cmu_rd()
1281 /* Configure the clock macro unit (CMU) clock type */ in xgene_phy_hw_init_sata()