Lines Matching +full:0 +full:xf
9 #define HDMI_CON0 0x00
11 #define RG_HDMITX_PLL_FBKDIV (0x7f << 24)
13 #define RG_HDMITX_PLL_FBKSEL (0x3 << 22)
15 #define RG_HDMITX_PLL_PREDIV (0x3 << 20)
17 #define RG_HDMITX_PLL_POSDIV (0x3 << 18)
19 #define RG_HDMITX_PLL_RST_DLY (0x3 << 16)
20 #define RG_HDMITX_PLL_IR (0xf << 12)
22 #define RG_HDMITX_PLL_IC (0xf << 8)
24 #define RG_HDMITX_PLL_BP (0xf << 4)
26 #define RG_HDMITX_PLL_BR (0x3 << 2)
28 #define RG_HDMITX_PLL_BC (0x3 << 0)
29 #define PLL_BC_SHIFT 0
30 #define HDMI_CON1 0x04
31 #define RG_HDMITX_PLL_DIVEN (0x7 << 29)
34 #define RG_HDMITX_PLL_AUTOK_KF (0x3 << 26)
35 #define RG_HDMITX_PLL_AUTOK_KS (0x3 << 24)
37 #define RG_HDMITX_PLL_BAND (0x3f << 16)
42 #define RG_HDMITX_PLL_TXDIV (0x3 << 10)
50 #define RG_HDMITX_PLL_TST_SEL (0xf << 0)
51 #define HDMI_CON2 0x08
52 #define RGS_HDMITX_PLL_AUTOK_BAND (0x7f << 8)
54 #define RG_HDMITX_EN_TX_CKLDO BIT(0)
55 #define HDMI_CON3 0x0c
56 #define RG_HDMITX_SER_EN (0xf << 28)
57 #define RG_HDMITX_PRD_EN (0xf << 24)
58 #define RG_HDMITX_PRD_IMP_EN (0xf << 20)
59 #define RG_HDMITX_DRV_EN (0xf << 16)
60 #define RG_HDMITX_DRV_IMP_EN (0xf << 12)
65 #define RG_HDMITX_SER_DIN_SEL (0xf << 4)
69 #define RG_HDMITX_SER_CLKDIG_INV BIT(0)
70 #define HDMI_CON4 0x10
71 #define RG_HDMITX_PRD_IBIAS_CLK (0xf << 24)
72 #define RG_HDMITX_PRD_IBIAS_D2 (0xf << 16)
73 #define RG_HDMITX_PRD_IBIAS_D1 (0xf << 8)
74 #define RG_HDMITX_PRD_IBIAS_D0 (0xf << 0)
78 #define PRD_IBIAS_D0_SHIFT 0
79 #define HDMI_CON5 0x14
80 #define RG_HDMITX_DRV_IBIAS_CLK (0x3f << 24)
81 #define RG_HDMITX_DRV_IBIAS_D2 (0x3f << 16)
82 #define RG_HDMITX_DRV_IBIAS_D1 (0x3f << 8)
83 #define RG_HDMITX_DRV_IBIAS_D0 (0x3f << 0)
87 #define DRV_IBIAS_D0_SHIFT 0
88 #define HDMI_CON6 0x18
89 #define RG_HDMITX_DRV_IMP_CLK (0x3f << 24)
90 #define RG_HDMITX_DRV_IMP_D2 (0x3f << 16)
91 #define RG_HDMITX_DRV_IMP_D1 (0x3f << 8)
92 #define RG_HDMITX_DRV_IMP_D0 (0x3f << 0)
96 #define DRV_IMP_D0_SHIFT 0
97 #define HDMI_CON7 0x1c
98 #define RG_HDMITX_MHLCK_DRV_IBIAS (0x1f << 27)
99 #define RG_HDMITX_SER_DIN (0x3ff << 16)
100 #define RG_HDMITX_CHLDC_TST (0xf << 12)
101 #define RG_HDMITX_CHLCK_TST (0xf << 8)
102 #define RG_HDMITX_RESERVE (0xff << 0)
103 #define HDMI_CON8 0x20
104 #define RGS_HDMITX_2T1_LEV (0xf << 16)
105 #define RGS_HDMITX_2T1_EDG (0xf << 12)
106 #define RGS_HDMITX_5T1_LEV (0xf << 8)
107 #define RGS_HDMITX_5T1_EDG (0xf << 4)
108 #define RGS_HDMITX_PLUG_TST BIT(0)
124 return 0; in mtk_hdmi_pll_prepare()
170 pre_div = 0; in mtk_hdmi_pll_set_rate()
184 (0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT), in mtk_hdmi_pll_set_rate()
189 (0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT), in mtk_hdmi_pll_set_rate()
192 (0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN); in mtk_hdmi_pll_set_rate()
194 (0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) | in mtk_hdmi_pll_set_rate()
195 (0x1 << PLL_BR_SHIFT), in mtk_hdmi_pll_set_rate()
201 pre_ibias = 0x3; in mtk_hdmi_pll_set_rate()
202 imp_en = 0x0; in mtk_hdmi_pll_set_rate()
207 pre_ibias = 0x6; in mtk_hdmi_pll_set_rate()
208 imp_en = 0xf; in mtk_hdmi_pll_set_rate()
239 return 0; in mtk_hdmi_pll_set_rate()