70 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_prepare()  local
72 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);  in mtk_hdmi_pll_prepare()
73 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);  in mtk_hdmi_pll_prepare()
74 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);  in mtk_hdmi_pll_prepare()
75 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);  in mtk_hdmi_pll_prepare()
77 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);  in mtk_hdmi_pll_prepare()
78 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);  in mtk_hdmi_pll_prepare()
79 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);  in mtk_hdmi_pll_prepare()
81 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);  in mtk_hdmi_pll_prepare()
82 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);  in mtk_hdmi_pll_prepare()
83 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);  in mtk_hdmi_pll_prepare()
84 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);  in mtk_hdmi_pll_prepare()
91 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_unprepare()  local
93 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);  in mtk_hdmi_pll_unprepare()
94 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);  in mtk_hdmi_pll_unprepare()
95 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);  in mtk_hdmi_pll_unprepare()
96 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);  in mtk_hdmi_pll_unprepare()
98 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);  in mtk_hdmi_pll_unprepare()
99 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);  in mtk_hdmi_pll_unprepare()
100 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);  in mtk_hdmi_pll_unprepare()
102 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);  in mtk_hdmi_pll_unprepare()
103 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);  in mtk_hdmi_pll_unprepare()
104 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);  in mtk_hdmi_pll_unprepare()
105 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);  in mtk_hdmi_pll_unprepare()
118 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_set_rate()  local
128 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK);  in mtk_hdmi_pll_set_rate()
129 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);  in mtk_hdmi_pll_set_rate()
130 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);  in mtk_hdmi_pll_set_rate()
131 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),  in mtk_hdmi_pll_set_rate()
133 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),  in mtk_hdmi_pll_set_rate()
135 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV),  in mtk_hdmi_pll_set_rate()
137 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),  in mtk_hdmi_pll_set_rate()
139 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),  in mtk_hdmi_pll_set_rate()
141 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN),  in mtk_hdmi_pll_set_rate()
143 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),  in mtk_hdmi_pll_set_rate()
145 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),  in mtk_hdmi_pll_set_rate()
147 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),  in mtk_hdmi_pll_set_rate()
150 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP);  in mtk_hdmi_pll_set_rate()
151 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS),  in mtk_hdmi_pll_set_rate()
153 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK);  in mtk_hdmi_pll_set_rate()
154 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP),  in mtk_hdmi_pll_set_rate()
156 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);  in mtk_hdmi_pll_set_rate()
157 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS),  in mtk_hdmi_pll_set_rate()
165 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_recalc_rate()  local
168 	val = (readl(hdmi_phy->regs + HDMI_CON6)  in mtk_hdmi_pll_recalc_rate()
182 	val = (readl(hdmi_phy->regs + HDMI_CON6)  in mtk_hdmi_pll_recalc_rate()
185 	val = (readl(hdmi_phy->regs + HDMI_CON2)  in mtk_hdmi_pll_recalc_rate()
189 	if (readl(hdmi_phy->regs + HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV)  in mtk_hdmi_pll_recalc_rate()
203 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)  in mtk_hdmi_phy_enable_tmds()  argument
205 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);  in mtk_hdmi_phy_enable_tmds()
206 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);  in mtk_hdmi_phy_enable_tmds()
207 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);  in mtk_hdmi_phy_enable_tmds()
208 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);  in mtk_hdmi_phy_enable_tmds()
210 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);  in mtk_hdmi_phy_enable_tmds()
211 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);  in mtk_hdmi_phy_enable_tmds()
212 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);  in mtk_hdmi_phy_enable_tmds()
214 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);  in mtk_hdmi_phy_enable_tmds()
215 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);  in mtk_hdmi_phy_enable_tmds()
216 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);  in mtk_hdmi_phy_enable_tmds()
217 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);  in mtk_hdmi_phy_enable_tmds()
221 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)  in mtk_hdmi_phy_disable_tmds()  argument
223 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);  in mtk_hdmi_phy_disable_tmds()
224 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);  in mtk_hdmi_phy_disable_tmds()
225 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);  in mtk_hdmi_phy_disable_tmds()
226 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);  in mtk_hdmi_phy_disable_tmds()
228 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);  in mtk_hdmi_phy_disable_tmds()
229 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);  in mtk_hdmi_phy_disable_tmds()
230 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);  in mtk_hdmi_phy_disable_tmds()
232 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);  in mtk_hdmi_phy_disable_tmds()
233 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);  in mtk_hdmi_phy_disable_tmds()
234 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);  in mtk_hdmi_phy_disable_tmds()
235 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);  in mtk_hdmi_phy_disable_tmds()