96 	struct mixel_dphy_cfg cfg;  member
156 	       struct mixel_dphy_cfg *cfg)  in mixel_dphy_config_from_opts()  argument
191 	cfg->cn = denominator >> i;  in mixel_dphy_config_from_opts()
192 	cfg->co = 1 << i;  in mixel_dphy_config_from_opts()
193 	cfg->cm = numerator;  in mixel_dphy_config_from_opts()
195 	if (cfg->cm < 16 || cfg->cm > 255 ||  in mixel_dphy_config_from_opts()
196 	    cfg->cn < 1 || cfg->cn > 32 ||  in mixel_dphy_config_from_opts()
197 	    cfg->co < 1 || cfg->co > 8) {  in mixel_dphy_config_from_opts()
199 			cfg->cm, cfg->cn, cfg->co);  in mixel_dphy_config_from_opts()
234 	cfg->m_prg_hs_prepare = n;  in mixel_dphy_config_from_opts()
244 	cfg->mc_prg_hs_prepare = dphy_opts->clk_prepare > lp_t ? 1 : 0;  in mixel_dphy_config_from_opts()
248 	cfg->m_prg_hs_zero = n < 1 ? 1 : n;  in mixel_dphy_config_from_opts()
252 	cfg->mc_prg_hs_zero = n < 1 ? 1 : n;  in mixel_dphy_config_from_opts()
260 	cfg->m_prg_hs_trail = n;  in mixel_dphy_config_from_opts()
261 	cfg->mc_prg_hs_trail = n;  in mixel_dphy_config_from_opts()
265 		cfg->rxhs_settle = 0x0d;  in mixel_dphy_config_from_opts()
267 		cfg->rxhs_settle = 0x0c;  in mixel_dphy_config_from_opts()
269 		cfg->rxhs_settle = 0x0b;  in mixel_dphy_config_from_opts()
271 		cfg->rxhs_settle = 0x0a;  in mixel_dphy_config_from_opts()
273 		cfg->rxhs_settle = 0x09;  in mixel_dphy_config_from_opts()
275 		cfg->rxhs_settle = 0x08;  in mixel_dphy_config_from_opts()
277 		cfg->rxhs_settle = 0x07;  in mixel_dphy_config_from_opts()
280 		cfg->m_prg_hs_prepare, cfg->mc_prg_hs_prepare,  in mixel_dphy_config_from_opts()
281 		cfg->m_prg_hs_zero, cfg->mc_prg_hs_zero,  in mixel_dphy_config_from_opts()
282 		cfg->m_prg_hs_trail, cfg->mc_prg_hs_trail,  in mixel_dphy_config_from_opts()
283 		cfg->rxhs_settle);  in mixel_dphy_config_from_opts()
292 	phy_write(phy, priv->cfg.m_prg_hs_prepare, DPHY_M_PRG_HS_PREPARE);  in mixel_phy_set_hs_timings()
293 	phy_write(phy, priv->cfg.mc_prg_hs_prepare, DPHY_MC_PRG_HS_PREPARE);  in mixel_phy_set_hs_timings()
294 	phy_write(phy, priv->cfg.m_prg_hs_zero, DPHY_M_PRG_HS_ZERO);  in mixel_phy_set_hs_timings()
295 	phy_write(phy, priv->cfg.mc_prg_hs_zero, DPHY_MC_PRG_HS_ZERO);  in mixel_phy_set_hs_timings()
296 	phy_write(phy, priv->cfg.m_prg_hs_trail, DPHY_M_PRG_HS_TRAIL);  in mixel_phy_set_hs_timings()
297 	phy_write(phy, priv->cfg.mc_prg_hs_trail, DPHY_MC_PRG_HS_TRAIL);  in mixel_phy_set_hs_timings()
298 	phy_write(phy, priv->cfg.rxhs_settle, priv->devdata->reg_rxhs_settle);  in mixel_phy_set_hs_timings()
305 	if (priv->cfg.cm < 16 || priv->cfg.cm > 255 ||  in mixel_dphy_set_pll_params()
306 	    priv->cfg.cn < 1 || priv->cfg.cn > 32 ||  in mixel_dphy_set_pll_params()
307 	    priv->cfg.co < 1 || priv->cfg.co > 8) {  in mixel_dphy_set_pll_params()
309 			priv->cfg.cm, priv->cfg.cn, priv->cfg.co);  in mixel_dphy_set_pll_params()
313 		priv->cfg.cm, priv->cfg.cn, priv->cfg.co);  in mixel_dphy_set_pll_params()
314 	phy_write(phy, CM(priv->cfg.cm), DPHY_CM);  in mixel_dphy_set_pll_params()
315 	phy_write(phy, CN(priv->cfg.cn), DPHY_CN);  in mixel_dphy_set_pll_params()
316 	phy_write(phy, CO(priv->cfg.co), DPHY_CO);  in mixel_dphy_set_pll_params()
323 	struct mixel_dphy_cfg cfg = { 0 };  in mixel_dphy_configure()  local
326 	ret = mixel_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);  in mixel_dphy_configure()
331 	memcpy(&priv->cfg, &cfg, sizeof(struct mixel_dphy_cfg));  in mixel_dphy_configure()
351 	struct mixel_dphy_cfg cfg = { 0 };  in mixel_dphy_validate()  local
356 	return mixel_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);  in mixel_dphy_validate()