Lines Matching +full:ati +full:- +full:target
1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
62 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
63 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
64 (f->vendor == dev->vendor || in pci_do_fixups()
65 f->vendor == (u16) PCI_ANY_ID) && in pci_do_fixups()
66 (f->device == dev->device || in pci_do_fixups()
67 f->device == (u16) PCI_ANY_ID)) { in pci_do_fixups()
70 hook = offset_to_ptr(&f->hook_offset); in pci_do_fixups()
72 hook = f->hook; in pci_do_fixups()
198 * key system devices. For devices that need to have mmio decoding always-on,
199 * we need to set the dev->mmio_always_on bit.
203 dev->mmio_always_on = 1; in quirk_mmio_always_on()
215 dev->broken_parity_status = 1; /* This device gives false positives */ in quirk_mellanox_tavor()
248 * contacts at VIA ask them for me please -- Alan
292 /* Chipsets where PCI->PCI transfers vanish or hang */
330 * Made according to a Windows driver-based patch by George E. Breese;
332 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
351 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; in quirk_vialatency()
355 if (p->revision < 0x40 || p->revision > 0x42) in quirk_vialatency()
363 if (p->revision < 0x10 || p->revision > 0x12) in quirk_vialatency()
455 dev->cfg_size = 0xA0; in quirk_citrine()
465 dev->cfg_size = 0x600; in quirk_nfp6000()
478 struct resource *r = &dev->resource[i]; in quirk_extend_bar_to_page()
480 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { in quirk_extend_bar_to_page()
481 r->end = PAGE_SIZE - 1; in quirk_extend_bar_to_page()
482 r->start = 0; in quirk_extend_bar_to_page()
483 r->flags |= IORESOURCE_UNSET; in quirk_extend_bar_to_page()
493 * If it's needed, re-allocate the region.
497 struct resource *r = &dev->resource[0]; in quirk_s3_64M()
499 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { in quirk_s3_64M()
500 r->flags |= IORESOURCE_UNSET; in quirk_s3_64M()
501 r->start = 0; in quirk_s3_64M()
502 r->end = 0x3ffffff; in quirk_s3_64M()
513 struct resource *res = dev->resource + pos; in quirk_io()
520 res->name = pci_name(dev); in quirk_io()
521 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; in quirk_io()
522 res->flags |= in quirk_io()
524 region &= ~(size - 1); in quirk_io()
528 bus_region.end = region + size - 1; in quirk_io()
529 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io()
541 * CS553x's ISA PCI BARs may also be read-only (ref:
542 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
563 struct resource *res = dev->resource + nr; in quirk_io_region()
566 region &= ~(size - 1); in quirk_io_region()
571 res->name = pci_name(dev); in quirk_io_region()
572 res->flags = IORESOURCE_IO; in quirk_io_region()
576 bus_region.end = region + size - 1; in quirk_io_region()
577 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io_region()
584 * ATI Northbridge setups MCE the processor if you even read somewhere
585 * between 0x3b0->0x3bb or read 0x3d3
589 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); in quirk_ati_exploding_mce()
609 u32 class = pdev->class; in quirk_amd_nl_class()
612 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_amd_nl_class()
613 …pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhc… in quirk_amd_nl_class()
614 class, pdev->class); in quirk_amd_nl_class()
622 * devices should use dwc3-haps driver. Change these devices' class code to
623 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
628 u32 class = pdev->class; in quirk_synopsys_haps()
630 switch (pdev->device) { in quirk_synopsys_haps()
634 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_synopsys_haps()
635 …pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhc… in quirk_synopsys_haps()
636 class, pdev->class); in quirk_synopsys_haps()
683 base &= -size; in piix4_io_quirk()
684 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); in piix4_io_quirk()
709 base &= -size; in piix4_mem_quirk()
710 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); in piix4_mem_quirk()
762 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
836 base &= ~(size-1); in ich6_lpc_generic_decode()
842 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); in ich6_lpc_generic_decode()
850 /* ICH6-specific generic IO decode */ in quirk_ich6_lpc()
869 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ in ich7_lpc_generic_decode()
881 /* ICH7-10 has the same common LPC generic IO decode registers */
913 if (dev->revision & 0x10) in quirk_vt82c586_acpi()
930 "vt82c686 HW-mon"); in quirk_vt82c686_acpi()
949 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
950 * back-to-back: Disable fast back-to-back on the secondary bus segment
957 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); in quirk_xio2000a()
958 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { in quirk_xio2000a()
972 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
975 * TODO: When we have device-specific interrupt routers, this code will go
985 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ in quirk_via_ioapic()
997 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
1009 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); in quirk_via_vt8237_bypass_apic_deassert()
1017 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1027 if (dev->revision >= 0x02) { in quirk_amd_ioapic()
1039 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ in quirk_cavium_sriov_rnm_link()
1040 if (dev->subsystem_device == 0xa118) in quirk_cavium_sriov_rnm_link()
1041 dev->sriov->link = dev->devfn; in quirk_cavium_sriov_rnm_link()
1048 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1052 if (dev->subordinate && dev->revision <= 0x12) { in quirk_amd_8131_mmrbc()
1053 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", in quirk_amd_8131_mmrbc()
1054 dev->revision); in quirk_amd_8131_mmrbc()
1055 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; in quirk_amd_8131_mmrbc()
1065 * -jgarzik
1075 d->irq = irq; in quirk_via_acpi()
1081 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1086 switch (dev->device) { in quirk_via_bridge()
1093 via_vlink_dev_lo = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1094 via_vlink_dev_hi = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1121 * quirk_via_vlink - VIA VLink IRQ number update
1136 if (via_vlink_dev_lo == -1) in quirk_via_vlink()
1139 new_irq = dev->irq; in quirk_via_vlink()
1146 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || in quirk_via_vlink()
1147 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) in quirk_via_vlink()
1172 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); in quirk_vt82c598_id()
1215 * DreamWorks-provided workaround for Dunord I-3000 problem
1223 struct resource *r = &dev->resource[1]; in quirk_dunord()
1225 r->flags |= IORESOURCE_UNSET; in quirk_dunord()
1226 r->start = 0; in quirk_dunord()
1227 r->end = 0xffffff; in quirk_dunord()
1232 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1234 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1238 dev->transparent = 1; in quirk_transparent_bridge()
1273 if (pdev->revision != 0x04) /* Only C0 requires this */ in quirk_disable_pxb()
1287 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ in quirk_amd_ide_mode()
1298 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; in quirk_amd_ide_mode()
1318 pdev->class &= ~5; in quirk_svwks_csb5ide()
1325 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1335 pdev->class &= ~5; in quirk_ide_samemode()
1344 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; in quirk_no_ata_d3()
1360 * This was originally an Alpha-specific thing, but it really fits here.
1361 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1365 dev->class = PCI_CLASS_BRIDGE_EISA << 8; in quirk_eisa_bridge()
1378 * becomes necessary to do this tweak in two steps -- the chosen trigger
1379 * is either the Host bridge (preferred) or on-board VGA controller.
1392 * the DSDT and double-check that there is no code accessing the SMBus.
1398 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_smbus_hostbridge()
1399 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) in asus_hides_smbus_hostbridge()
1400 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1401 case 0x8025: /* P4B-LX */ in asus_hides_smbus_hostbridge()
1407 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) in asus_hides_smbus_hostbridge()
1408 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1409 case 0x80b1: /* P4GE-V */ in asus_hides_smbus_hostbridge()
1411 case 0x8093: /* P4B533-V */ in asus_hides_smbus_hostbridge()
1414 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) in asus_hides_smbus_hostbridge()
1415 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1419 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) in asus_hides_smbus_hostbridge()
1420 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1424 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) in asus_hides_smbus_hostbridge()
1425 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1426 case 0x80c9: /* PU-DLS */ in asus_hides_smbus_hostbridge()
1429 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) in asus_hides_smbus_hostbridge()
1430 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1436 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1437 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1442 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1443 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1444 case 0x80f2: /* P4P800-X */ in asus_hides_smbus_hostbridge()
1447 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) in asus_hides_smbus_hostbridge()
1448 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1453 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { in asus_hides_smbus_hostbridge()
1454 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1455 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1460 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1461 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1467 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) in asus_hides_smbus_hostbridge()
1468 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1472 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { in asus_hides_smbus_hostbridge()
1473 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1474 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1478 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { in asus_hides_smbus_hostbridge()
1479 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1480 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1484 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) in asus_hides_smbus_hostbridge()
1485 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1486 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ in asus_hides_smbus_hostbridge()
1489 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1492 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) in asus_hides_smbus_hostbridge()
1493 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1498 * subvendor/subdevice IDs and on-board VGA in asus_hides_smbus_hostbridge()
1504 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) in asus_hides_smbus_hostbridge()
1505 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1509 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1661 dev->device = devid; in quirk_sis_503()
1671 * -- bjd
1678 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_ac97_lpc()
1679 if (dev->device == PCI_DEVICE_ID_VIA_8237) in asus_hides_ac97_lpc()
1712 if (PCI_FUNC(pdev->devfn)) in quirk_jmicron_ata()
1718 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ in quirk_jmicron_ata()
1721 switch (pdev->device) { in quirk_jmicron_ata()
1753 pdev->hdr_type = hdr & 0x7f; in quirk_jmicron_ata()
1754 pdev->multifunction = !!(hdr & 0x80); in quirk_jmicron_ata()
1757 pdev->class = class >> 8; in quirk_jmicron_ata()
1782 if (dev->multifunction) { in quirk_jmicron_async_suspend()
1783 device_disable_async_suspend(&dev->dev); in quirk_jmicron_async_suspend()
1784 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); in quirk_jmicron_async_suspend()
1797 if ((pdev->class >> 8) != 0xff00) in quirk_alder_ioapic()
1801 * The first BAR is the location of the IO-APIC... we must in quirk_alder_ioapic()
1806 insert_resource(&iomem_resource, &pdev->resource[0]); in quirk_alder_ioapic()
1813 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); in quirk_alder_ioapic()
1820 pdev->no_msi = 1; in quirk_pcie_mch()
1830 * together on certain PXH-based systems.
1834 dev->no_msi = 1; in quirk_pcie_pxh()
1850 dev->no_d1d2 = 1; in quirk_intel_pcie_pm()
1876 if (dev->d3hot_delay >= delay) in quirk_d3hot_delay()
1879 dev->d3hot_delay = delay; in quirk_d3hot_delay()
1880 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", in quirk_d3hot_delay()
1881 dev->d3hot_delay); in quirk_d3hot_delay()
1886 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && in quirk_radeon_pm()
1887 dev->subsystem_device == 0x00e2) in quirk_radeon_pm()
1898 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1912 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); in dmi_disable_ioapicreroute()
1923 .ident = "ASUSTek Computer INC. M2N-LR",
1926 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1944 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; in quirk_reroute_to_boot_interrupts_intel()
1946 dev->vendor, dev->device); in quirk_reroute_to_boot_interrupts_intel()
1971 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1972 * 300641-004US, section 5.7.3.
1974 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
1975 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
1976 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
1977 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
1978 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
1979 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
1980 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
1981 * Core IO on Xeon D-1500, see Intel order no 332051-001.
1998 switch (dev->device) { in quirk_disable_intel_boot_interrupt()
2009 case 0x6f28: /* Xeon D-1500 */ in quirk_disable_intel_boot_interrupt()
2021 dev->vendor, dev->device); in quirk_disable_intel_boot_interrupt()
2024 * Device 29 Func 5 Device IDs of IO-APIC
2060 /* Disable boot interrupts on HT-1000 */
2086 dev->vendor, dev->device); in quirk_disable_broadcom_boot_interrupt()
2091 /* Disable boot interrupts on AMD and ATI chipsets */
2095 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2109 if ((dev->revision == AMD_813X_REV_B1) || in quirk_disable_amd_813x_boot_interrupt()
2110 (dev->revision == AMD_813X_REV_B2)) in quirk_disable_amd_813x_boot_interrupt()
2118 dev->vendor, dev->device); in quirk_disable_amd_813x_boot_interrupt()
2137 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2142 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2149 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2151 * Re-allocate the region if needed...
2155 struct resource *r = &dev->resource[0]; in quirk_tc86c001_ide()
2157 if (r->start & 0x8) { in quirk_tc86c001_ide()
2158 r->flags |= IORESOURCE_UNSET; in quirk_tc86c001_ide()
2159 r->start = 0; in quirk_tc86c001_ide()
2160 r->end = 0xf; in quirk_tc86c001_ide()
2168 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2172 * Re-allocate the regions to a 256-byte boundary if necessary.
2179 if (dev->revision >= 2) in quirk_plx_pci9050()
2184 struct resource *r = &dev->resource[bar]; in quirk_plx_pci9050()
2185 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", in quirk_plx_pci9050()
2187 r->flags |= IORESOURCE_UNSET; in quirk_plx_pci9050()
2188 r->start = 0; in quirk_plx_pci9050()
2189 r->end = 0xff; in quirk_plx_pci9050()
2208 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; in quirk_netmos()
2209 unsigned int num_serial = dev->subsystem_device & 0xf; in quirk_netmos()
2221 switch (dev->device) { in quirk_netmos()
2224 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && in quirk_netmos()
2225 dev->subsystem_device == 0x0299) in quirk_netmos()
2234 dev->device, num_parallel, num_serial); in quirk_netmos()
2235 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | in quirk_netmos()
2236 (dev->class & 0xff); in quirk_netmos()
2249 switch (dev->device) { in quirk_e100_interrupt()
2274 * re-enable them when it's ready. in quirk_e100_interrupt()
2285 if (dev->pm_cap) { in quirk_e100_interrupt()
2286 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in quirk_e100_interrupt()
2340 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2347 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2356 dev->clear_retrain_link = 1; in quirk_enable_clear_retrain_link()
2365 u32 class = dev->class; in fixup_rev1_53c810()
2374 dev->class = PCI_CLASS_STORAGE_SCSI << 8; in fixup_rev1_53c810()
2375 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", in fixup_rev1_53c810()
2376 class, dev->class); in fixup_rev1_53c810()
2389 dev->io_window_1k = 1; in quirk_p64h2_1k_io()
2423 * VT6212L is found -- the CX700 core itself also contains a USB in quirk_via_cx700_pci_parking_caching()
2433 * p should contain the first (internal) VT6212L -- see if we have in quirk_via_cx700_pci_parking_caching()
2455 /* Set PCI Master Bus time-out to "1x16 PCLK" */ in quirk_via_cx700_pci_parking_caching()
2487 * DRBs - this is where we expose device 6.
2488 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2529 if (dev->subordinate) { in quirk_disable_msi()
2531 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_disable_msi()
2548 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); in quirk_amd_780_apc_msi()
2550 if (apc_bridge->device == 0x9602) in quirk_amd_780_apc_msi()
2567 while (pos && ttl--) { in msi_ht_cap_enabled()
2587 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { in quirk_msi_ht_cap()
2589 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_msi_ht_cap()
2603 if (!dev->subordinate) in quirk_nvidia_ck804_msi_ht_cap()
2610 pdev = pci_get_slot(dev->bus, 0); in quirk_nvidia_ck804_msi_ht_cap()
2615 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_nvidia_ck804_msi_ht_cap()
2628 while (pos && ttl--) { in ht_enable_msi_mapping()
2649 * The P5N32-SLI motherboards from Asus have a problem with MSI
2658 (strstr(board_name, "P5N32-SLI PREMIUM") || in nvenet_msi_disable()
2659 strstr(board_name, "P5N32-E SLI"))) { in nvenet_msi_disable()
2660 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); in nvenet_msi_disable()
2661 dev->no_msi = 1; in nvenet_msi_disable()
2669 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2674 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2679 dev->no_msi = 1; in pci_quirk_nvidia_tegra_disable_rp_msi()
2760 while (pos && ttl--) { in ht_check_msi_mapping()
2788 dev_no = host_bridge->devfn >> 3; in host_bridge_with_leaf()
2790 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); in host_bridge_with_leaf()
2846 dev_no = dev->devfn >> 3; in nv_ht_enable_msi_mapping()
2847 for (i = dev_no; i >= 0; i--) { in nv_ht_enable_msi_mapping()
2848 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); in nv_ht_enable_msi_mapping()
2883 while (pos && ttl--) { in ht_disable_msi_mapping()
2916 * a non-Hypertransport host bridge. Locate the host bridge... in __nv_msi_ht_cap_quirk()
2918 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, in __nv_msi_ht_cap_quirk()
2965 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_bug()
2982 if ((p->revision < 0x3B) && (p->revision >= 0x30)) in quirk_msi_intx_disable_ati_bug()
2983 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_ati_bug()
2990 if (dev->revision < 0x18) { in quirk_msi_intx_disable_qca_bug()
2992 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_qca_bug()
3056 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3060 * tested), since currently there is no standard way to disable only MSI-X.
3067 dev->no_msi = 1; in quirk_al_msi_disable()
3068 pci_warn(dev, "Disabling MSI/MSI-X\n"); in quirk_al_msi_disable()
3076 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3083 dev->is_hotplug_bridge = 1; in quirk_hotplug_bridge()
3100 * MMC controller - so the SDHCI driver never sees them.
3124 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_rl5c476()
3155 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_r5c832()
3162 * 0x150 - SD2.0 mode enable for changing base clock in ricoh_mmc_fixup_r5c832()
3164 * 0xe1 - Base clock frequency in ricoh_mmc_fixup_r5c832()
3165 * 0x32 - 50Mhz new clock frequency in ricoh_mmc_fixup_r5c832()
3166 * 0xf9 - Key register for 0x150 in ricoh_mmc_fixup_r5c832()
3167 * 0xfc - key register for 0xe1 in ricoh_mmc_fixup_r5c832()
3169 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || in ricoh_mmc_fixup_r5c832()
3170 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { in ricoh_mmc_fixup_r5c832()
3207 * This is a quirk for masking VT-d spec-defined errors to platform error
3210 * on the RAS config settings of the platform) when a VT-d fault happens.
3213 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3229 u32 class = dev->class; in fixup_ti816x_class()
3232 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; in fixup_ti816x_class()
3233 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", in fixup_ti816x_class()
3234 class, dev->class); in fixup_ti816x_class()
3245 dev->pcie_mpss = 1; /* 256 bytes */ in fixup_mpss_256()
3259 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3295 /* Intel 5000 series memory controllers and ports 2-7 */
3310 /* Intel 5100 series memory controllers and ports 2-7 */
3337 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3343 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3352 * and the interrupt ends up -somewhere-.
3392 dev->d3hot_delay = 0; in quirk_remove_d3hot_delay()
3398 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3428 dev->broken_intx_masking = 1; in quirk_broken_intx_masking()
3441 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3448 * DisINTx can be set but the interrupt status bit is non-functional.
3488 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3504 if (pdev->device == mellanox_broken_intx_devs[i]) { in mellanox_check_broken_intx_masking()
3505 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3511 * Getting here means Connect-IB cards and up. Connect-IB has no INTx in mellanox_check_broken_intx_masking()
3514 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) in mellanox_check_broken_intx_masking()
3517 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && in mellanox_check_broken_intx_masking()
3518 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) in mellanox_check_broken_intx_masking()
3521 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ in mellanox_check_broken_intx_masking()
3529 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); in mellanox_check_broken_intx_masking()
3541 …pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW… in mellanox_check_broken_intx_masking()
3542 fw_major, fw_minor, fw_subminor, pdev->device == in mellanox_check_broken_intx_masking()
3544 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3557 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; in quirk_no_bus_reset()
3562 * The device will throw a Link Down error on AER-capable systems and
3586 if (!pci_is_root_bus(dev->bus)) in quirk_no_pm_reset()
3587 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; in quirk_no_pm_reset()
3591 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3592 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3608 if (pdev->is_hotplug_bridge && in quirk_thunderbolt_hotplug_msi()
3609 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || in quirk_thunderbolt_hotplug_msi()
3610 pdev->revision <= 1)) in quirk_thunderbolt_hotplug_msi()
3611 pdev->no_msi = 1; in quirk_thunderbolt_hotplug_msi()
3648 bridge = ACPI_HANDLE(&dev->dev); in quirk_apple_poweroff_thunderbolt()
3679 * Following are device-specific reset methods which can be used to
3680 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3686 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf in reset_intel_82599_sfp_virtfn()
3716 return -ENOMEM; in reset_ivb_igd()
3747 /* Device-specific reset method for Chelsio T4-based adapters */
3754 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating in reset_chelsio_generic_dev()
3755 * that we have no device-specific reset method. in reset_chelsio_generic_dev()
3757 if ((dev->device & 0xf000) != 0x4000) in reset_chelsio_generic_dev()
3758 return -ENOTTY; in reset_chelsio_generic_dev()
3784 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts in reset_chelsio_generic_dev()
3785 * are disabled when an MSI-X interrupt message needs to be delivered. in reset_chelsio_generic_dev()
3786 * So we briefly re-enable MSI-X interrupts for the duration of the in reset_chelsio_generic_dev()
3788 * MSI-X state. in reset_chelsio_generic_dev()
3790 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); in reset_chelsio_generic_dev()
3792 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, in reset_chelsio_generic_dev()
3815 * FLR where config space reads from the device return -1. We seem to be
3832 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || in nvme_disable_and_flr()
3834 return -ENOTTY; in nvme_disable_and_flr()
3841 return -ENOTTY; in nvme_disable_and_flr()
3903 return -ENOTTY; in delay_250ms_after_flr()
3930 * These device-specific reset methods are here rather than in a driver
3938 for (i = pci_dev_reset_methods; i->reset; i++) { in pci_dev_specific_reset()
3939 if ((i->vendor == dev->vendor || in pci_dev_specific_reset()
3940 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_reset()
3941 (i->device == dev->device || in pci_dev_specific_reset()
3942 i->device == (u16)PCI_ANY_ID)) in pci_dev_specific_reset()
3943 return i->reset(dev, probe); in pci_dev_specific_reset()
3946 return -ENOTTY; in pci_dev_specific_reset()
3951 if (PCI_FUNC(dev->devfn) != 0) in quirk_dma_func0_alias()
3952 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); in quirk_dma_func0_alias()
3965 if (PCI_FUNC(dev->devfn) != 1) in quirk_dma_func1_alias()
3966 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); in quirk_dma_func1_alias()
4016 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4026 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4051 pci_add_dma_alias(dev, id->driver_data, 1); in quirk_fixed_dma_alias()
4056 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4061 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4062 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4066 if (!pci_is_root_bus(pdev->bus) && in quirk_use_pcie_bridge_dma_alias()
4067 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && in quirk_use_pcie_bridge_dma_alias()
4068 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && in quirk_use_pcie_bridge_dma_alias()
4069 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) in quirk_use_pcie_bridge_dma_alias()
4070 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; in quirk_use_pcie_bridge_dma_alias()
4087 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4100 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4135 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; in quirk_bridge_cavm_thrx2_pcie_root()
4143 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4148 u32 class = pdev->class; in quirk_tw686x_class()
4151 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; in quirk_tw686x_class()
4152 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", in quirk_tw686x_class()
4153 class, pdev->class); in quirk_tw686x_class()
4171 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; in quirk_relaxedordering_disable()
4258 * If a non-compliant device generates a completion with a different
4260 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4264 * If the non-compliant device generates completions with zero attributes
4286 dev_name(&pdev->dev)); in quirk_disable_root_port_attributes()
4304 if ((pdev->device & 0xff00) == 0x5400) in quirk_chelsio_T5_disable_root_port_attributes()
4311 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4329 * AMD has indicated that the devices below do not support peer-to-peer
4332 * peer-to-peer between functions can claim to support a subset of ACS.
4360 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) in pci_quirk_amd_sb_acs()
4361 return -ENODEV; in pci_quirk_amd_sb_acs()
4366 return -ENODEV; in pci_quirk_amd_sb_acs()
4375 return -ENODEV; in pci_quirk_amd_sb_acs()
4384 switch (dev->device) { in pci_quirk_cavium_acs_match()
4401 return -ENOTTY; in pci_quirk_cavium_acs()
4418 * X-Gene Root Ports matching this quirk do not allow peer-to-peer in pci_quirk_xgene_acs()
4428 * But the implementation could block peer-to-peer transactions between them
4429 * and provide ACS-like functionality.
4436 return -ENOTTY; in pci_quirk_zhaoxin_pcie_ports_acs()
4438 switch (dev->device) { in pci_quirk_zhaoxin_pcie_ports_acs()
4450 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4465 /* Lynxpoint-H PCH */
4468 /* Lynxpoint-LP PCH */
4487 /* Filter out a few obvious non-matches first */ in pci_quirk_intel_pch_acs_match()
4492 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) in pci_quirk_intel_pch_acs_match()
4501 return -ENOTTY; in pci_quirk_intel_pch_acs()
4503 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) in pci_quirk_intel_pch_acs()
4511 * These QCOM Root Ports do provide ACS-like features to disable peer
4515 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4529 return -ENOTTY; in pci_quirk_al_acs()
4533 * but do include ACS-like functionality. The hardware doesn't support in pci_quirk_al_acs()
4534 * peer-to-peer transactions via the root port and each has a unique in pci_quirk_al_acs()
4554 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4555 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4563 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4567 * 0xa290-0xa29f PCI Express Root port #{0-16}
4568 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4574 * August 2017, Revision 002, Document#: 334660-002)[6]
4577 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4579 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4581 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4582 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4583 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4584 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4585 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4586 …ww.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-…
4587 …tel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datas…
4594 switch (dev->device) { in pci_quirk_intel_spt_pch_acs_match()
4612 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4614 pos = dev->acs_cap; in pci_quirk_intel_spt_pch_acs()
4616 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4633 * in their ACS capability if they support peer-to-peer transactions. in pci_quirk_mf_endpoint_acs()
4635 * perform peer-to-peer with other functions, allowing us to mask out in pci_quirk_mf_endpoint_acs()
4647 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, in pci_quirk_rciep_acs()
4648 * "Root-Complex Peer to Peer Considerations". in pci_quirk_rciep_acs()
4651 return -ENOTTY; in pci_quirk_rciep_acs()
4661 * they do not allow peer-to-peer transactions between Root Ports. in pci_quirk_brcm_acs()
4731 /* 82571 (Quads omitted due to non-ACS switch) */
4748 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4749 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4752 /* APM X-Gene */
4766 /* Zhaoxin multi-function devices */
4776 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4781 * -ENOTTY: No quirk applies to this device; we can't tell whether the
4793 * or control to indicate their support here. Multi-function express in pci_dev_specific_acs_enabled()
4794 * devices which do not allow internal peer-to-peer between functions, in pci_dev_specific_acs_enabled()
4797 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { in pci_dev_specific_acs_enabled()
4798 if ((i->vendor == dev->vendor || in pci_dev_specific_acs_enabled()
4799 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_acs_enabled()
4800 (i->device == dev->device || in pci_dev_specific_acs_enabled()
4801 i->device == (u16)PCI_ANY_ID)) { in pci_dev_specific_acs_enabled()
4802 ret = i->acs_enabled(dev, acs_flags); in pci_dev_specific_acs_enabled()
4808 return -ENOTTY; in pci_dev_specific_acs_enabled()
4820 /* Backbone Peer Non-Posted Disable */
4840 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), in pci_quirk_enable_intel_lpc_acs()
4843 return -EINVAL; in pci_quirk_enable_intel_lpc_acs()
4848 return -ENOMEM; in pci_quirk_enable_intel_lpc_acs()
4852 * therefore read-only. If both posted and non-posted peer cycles are in pci_quirk_enable_intel_lpc_acs()
4900 * if dev->external_facing || dev->untrusted
4905 return -ENOTTY; in pci_quirk_enable_intel_pch_acs()
4914 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; in pci_quirk_enable_intel_pch_acs()
4927 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
4929 pos = dev->acs_cap; in pci_quirk_enable_intel_spt_pch_acs()
4931 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
4941 if (dev->external_facing || dev->untrusted) in pci_quirk_enable_intel_spt_pch_acs()
4957 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
4959 pos = dev->acs_cap; in pci_quirk_disable_intel_spt_pch_acs_redir()
4961 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
4997 if ((p->vendor == dev->vendor || in pci_dev_specific_enable_acs()
4998 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
4999 (p->device == dev->device || in pci_dev_specific_enable_acs()
5000 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5001 p->enable_acs) { in pci_dev_specific_enable_acs()
5002 ret = p->enable_acs(dev); in pci_dev_specific_enable_acs()
5008 return -ENOTTY; in pci_dev_specific_enable_acs()
5018 if ((p->vendor == dev->vendor || in pci_dev_specific_disable_acs_redir()
5019 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5020 (p->device == dev->device || in pci_dev_specific_disable_acs_redir()
5021 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5022 p->disable_acs_redir) { in pci_dev_specific_disable_acs_redir()
5023 ret = p->disable_acs_redir(dev); in pci_dev_specific_disable_acs_redir()
5029 return -ENOTTY; in pci_dev_specific_disable_acs_redir()
5047 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) in quirk_intel_qat_vf_cap()
5067 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() in quirk_intel_qat_vf_cap()
5080 pdev->pcie_cap = pos; in quirk_intel_qat_vf_cap()
5082 pdev->pcie_flags_reg = reg16; in quirk_intel_qat_vf_cap()
5084 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; in quirk_intel_qat_vf_cap()
5086 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; in quirk_intel_qat_vf_cap()
5089 pdev->cfg_size = PCI_CFG_SPACE_SIZE; in quirk_intel_qat_vf_cap()
5099 state->cap.cap_nr = PCI_CAP_ID_EXP; in quirk_intel_qat_vf_cap()
5100 state->cap.cap_extended = 0; in quirk_intel_qat_vf_cap()
5101 state->cap.size = size; in quirk_intel_qat_vf_cap()
5102 cap = (u16 *)&state->cap.data[0]; in quirk_intel_qat_vf_cap()
5110 hlist_add_head(&state->next, &pdev->saved_cap_space); in quirk_intel_qat_vf_cap()
5127 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; in quirk_no_flr()
5137 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); in quirk_no_ext_tags()
5142 bridge->no_ext_tags = 1; in quirk_no_ext_tags()
5145 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); in quirk_no_ext_tags()
5163 if ((pdev->device == 0x7312 && pdev->revision != 0x00) || in quirk_amd_harvest_no_ats()
5164 (pdev->device == 0x7340 && pdev->revision != 0xc5)) in quirk_amd_harvest_no_ats()
5168 pdev->ats_cap = 0; in quirk_amd_harvest_no_ats()
5185 pdev->no_msi = 1; in quirk_fsl_no_msi()
5190 * Although not allowed by the spec, some multi-function devices have
5203 if (PCI_FUNC(pdev->devfn) != consumer) in pci_create_device_link()
5206 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), in pci_create_device_link()
5207 pdev->bus->number, in pci_create_device_link()
5208 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); in pci_create_device_link()
5209 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { in pci_create_device_link()
5214 if (device_link_add(&pdev->dev, &supplier_pdev->dev, in pci_create_device_link()
5222 pm_runtime_allow(&pdev->dev); in pci_create_device_link()
5253 * Create device link for NVIDIA GPU with integrated Type-C UCSI controller
5277 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) in quirk_nvidia_hda()
5288 /* The GPU becomes a multi-function device when the HDA is enabled */ in quirk_nvidia_hda()
5290 gpu->multifunction = !!(hdr_type & 0x80); in quirk_nvidia_hda()
5301 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5303 * Item #36 - Downstream port applies ACS Source Validation to Completions
5316 * write, so we do config reads until we receive a non-Config Request Retry
5327 struct pci_dev *bridge = bus->self; in pci_idt_bus_quirk()
5329 pos = bridge->acs_cap; in pci_idt_bus_quirk()
5341 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ in pci_idt_bus_quirk()
5345 /* Re-enable ACS_SV if it was previously enabled */ in pci_idt_bus_quirk()
5385 partition = ioread8(&mmio_ntb->partition_id); in quirk_switchtec_ntb_dma_alias()
5387 partition_map = ioread32(&mmio_ntb->ep_map); in quirk_switchtec_ntb_dma_alias()
5388 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; in quirk_switchtec_ntb_dma_alias()
5403 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); in quirk_switchtec_ntb_dma_alias()
5420 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); in quirk_switchtec_ntb_dma_alias()
5521 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5522 pdev->subsystem_device != 0x222e || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5523 !pdev->reset_fn) in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5565 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); in pci_fixup_no_d0_pme()
5577 dev->pme_support = 0; in pci_fixup_no_pme()
5584 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; in apex_pci_fixup_class()