74 static int dpc_wait_rp_inactive(struct pci_dev *pdev)  in dpc_wait_rp_inactive()  argument
77 	u16 cap = pdev->dpc_cap, status;  in dpc_wait_rp_inactive()
79 	pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);  in dpc_wait_rp_inactive()
83 		pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);  in dpc_wait_rp_inactive()
86 		pci_warn(pdev, "root port still busy\n");  in dpc_wait_rp_inactive()
92 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)  in dpc_reset_link()  argument
100 	cap = pdev->dpc_cap;  in dpc_reset_link()
106 	if (!pcie_wait_for_link(pdev, false))  in dpc_reset_link()
107 		pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n");  in dpc_reset_link()
109 	if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev))  in dpc_reset_link()
112 	pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,  in dpc_reset_link()
115 	if (!pcie_wait_for_link(pdev, true)) {  in dpc_reset_link()
116 		pci_info(pdev, "Data Link Layer Link Active not set in 1000 msec\n");  in dpc_reset_link()
123 static void dpc_process_rp_pio_error(struct pci_dev *pdev)  in dpc_process_rp_pio_error()  argument
125 	u16 cap = pdev->dpc_cap, dpc_status, first_error;  in dpc_process_rp_pio_error()
129 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);  in dpc_process_rp_pio_error()
130 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);  in dpc_process_rp_pio_error()
131 	pci_err(pdev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",  in dpc_process_rp_pio_error()
134 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);  in dpc_process_rp_pio_error()
135 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);  in dpc_process_rp_pio_error()
136 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);  in dpc_process_rp_pio_error()
137 	pci_err(pdev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",  in dpc_process_rp_pio_error()
141 	pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);  in dpc_process_rp_pio_error()
146 			pci_err(pdev, "[%2d] %s%s\n", i, rp_pio_error_string[i],  in dpc_process_rp_pio_error()
150 	if (pdev->dpc_rp_log_size < 4)  in dpc_process_rp_pio_error()
152 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,  in dpc_process_rp_pio_error()
154 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,  in dpc_process_rp_pio_error()
156 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,  in dpc_process_rp_pio_error()
158 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,  in dpc_process_rp_pio_error()
160 	pci_err(pdev, "TLP Header: %#010x %#010x %#010x %#010x\n",  in dpc_process_rp_pio_error()
163 	if (pdev->dpc_rp_log_size < 5)  in dpc_process_rp_pio_error()
165 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);  in dpc_process_rp_pio_error()
166 	pci_err(pdev, "RP PIO ImpSpec Log %#010x\n", log);  in dpc_process_rp_pio_error()
168 	for (i = 0; i < pdev->dpc_rp_log_size - 5; i++) {  in dpc_process_rp_pio_error()
169 		pci_read_config_dword(pdev,  in dpc_process_rp_pio_error()
171 		pci_err(pdev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);  in dpc_process_rp_pio_error()
174 	pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status);  in dpc_process_rp_pio_error()
199 void dpc_process_error(struct pci_dev *pdev)  in dpc_process_error()  argument
201 	u16 cap = pdev->dpc_cap, status, source, reason, ext_reason;  in dpc_process_error()
204 	pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);  in dpc_process_error()
205 	pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source);  in dpc_process_error()
207 	pci_info(pdev, "containment event, status:%#06x source:%#06x\n",  in dpc_process_error()
212 	pci_warn(pdev, "%s detected\n",  in dpc_process_error()
221 	if (pdev->dpc_rp_extensions && reason == 3 && ext_reason == 0)  in dpc_process_error()
222 		dpc_process_rp_pio_error(pdev);  in dpc_process_error()
224 		 dpc_get_aer_uncorrect_severity(pdev, &info) &&  in dpc_process_error()
225 		 aer_get_device_error_info(pdev, &info)) {  in dpc_process_error()
226 		aer_print_error(pdev, &info);  in dpc_process_error()
227 		pci_aer_clear_nonfatal_status(pdev);  in dpc_process_error()
228 		pci_aer_clear_fatal_status(pdev);  in dpc_process_error()
234 	struct pci_dev *pdev = context;  in dpc_handler()  local
236 	dpc_process_error(pdev);  in dpc_handler()
239 	pcie_do_recovery(pdev, pci_channel_io_frozen, dpc_reset_link);  in dpc_handler()
246 	struct pci_dev *pdev = context;  in dpc_irq()  local
247 	u16 cap = pdev->dpc_cap, status;  in dpc_irq()
249 	pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);  in dpc_irq()
254 	pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,  in dpc_irq()
261 void pci_dpc_init(struct pci_dev *pdev)  in pci_dpc_init()  argument
265 	pdev->dpc_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);  in pci_dpc_init()
266 	if (!pdev->dpc_cap)  in pci_dpc_init()
269 	pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);  in pci_dpc_init()
273 	pdev->dpc_rp_extensions = true;  in pci_dpc_init()
274 	pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;  in pci_dpc_init()
275 	if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {  in pci_dpc_init()
276 		pci_err(pdev, "RP PIO log size %u is invalid\n",  in pci_dpc_init()
277 			pdev->dpc_rp_log_size);  in pci_dpc_init()
278 		pdev->dpc_rp_log_size = 0;  in pci_dpc_init()
285 	struct pci_dev *pdev = dev->port;  in dpc_probe()  local
290 	if (!pcie_aer_is_native(pdev) && !pcie_ports_dpc_native)  in dpc_probe()
295 					   "pcie-dpc", pdev);  in dpc_probe()
297 		pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq,  in dpc_probe()
302 	pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);  in dpc_probe()
303 	pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);  in dpc_probe()
306 	pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);  in dpc_probe()
307 	pci_info(pdev, "enabled with IRQ %d\n", dev->irq);  in dpc_probe()
309 …pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP …  in dpc_probe()
312 		 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), pdev->dpc_rp_log_size,  in dpc_probe()
315 	pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16));  in dpc_probe()
321 	struct pci_dev *pdev = dev->port;  in dpc_remove()  local
324 	pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);  in dpc_remove()
326 	pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);  in dpc_remove()