Lines Matching +full:parent +full:- +full:child
1 // SPDX-License-Identifier: GPL-2.0
53 struct pcie_link_state *parent; /* pointer to the parent Link state */ member
121 return link->aspm_default; in policy_to_aspm_state()
137 return link->clkpm_default; in policy_to_clkpm_state()
144 struct pci_dev *child; in pcie_set_clkpm_nocheck() local
145 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_set_clkpm_nocheck()
148 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_set_clkpm_nocheck()
149 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL, in pcie_set_clkpm_nocheck()
152 link->clkpm_enabled = !!enable; in pcie_set_clkpm_nocheck()
161 if (!link->clkpm_capable || link->clkpm_disable) in pcie_set_clkpm()
164 if (link->clkpm_enabled == enable) in pcie_set_clkpm()
174 struct pci_dev *child; in pcie_clkpm_cap_init() local
175 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_clkpm_cap_init()
178 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_clkpm_cap_init()
179 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); in pcie_clkpm_cap_init()
185 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); in pcie_clkpm_cap_init()
189 link->clkpm_enabled = enabled; in pcie_clkpm_cap_init()
190 link->clkpm_default = enabled; in pcie_clkpm_cap_init()
191 link->clkpm_capable = capable; in pcie_clkpm_cap_init()
192 link->clkpm_disable = blacklist ? 1 : 0; in pcie_clkpm_cap_init()
197 struct pci_dev *parent = link->pdev; in pcie_retrain_link() local
201 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); in pcie_retrain_link()
203 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); in pcie_retrain_link()
204 if (parent->clear_retrain_link) { in pcie_retrain_link()
211 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); in pcie_retrain_link()
217 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); in pcie_retrain_link()
234 struct pci_dev *child, *parent = link->pdev; in pcie_aspm_configure_common_clock() local
235 struct pci_bus *linkbus = parent->subordinate; in pcie_aspm_configure_common_clock()
240 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); in pcie_aspm_configure_common_clock()
241 BUG_ON(!pci_is_pcie(child)); in pcie_aspm_configure_common_clock()
244 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16); in pcie_aspm_configure_common_clock()
249 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); in pcie_aspm_configure_common_clock()
254 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); in pcie_aspm_configure_common_clock()
258 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_configure_common_clock()
259 pcie_capability_read_word(child, PCI_EXP_LNKCTL, in pcie_aspm_configure_common_clock()
268 pci_info(parent, "ASPM: current common clock configuration is inconsistent, reconfiguring\n"); in pcie_aspm_configure_common_clock()
272 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_configure_common_clock()
273 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); in pcie_aspm_configure_common_clock()
274 child_reg[PCI_FUNC(child->devfn)] = reg16; in pcie_aspm_configure_common_clock()
279 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16); in pcie_aspm_configure_common_clock()
283 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); in pcie_aspm_configure_common_clock()
289 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); in pcie_aspm_configure_common_clock()
295 pci_err(parent, "ASPM: Could not configure common clock\n"); in pcie_aspm_configure_common_clock()
296 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_aspm_configure_common_clock()
297 pcie_capability_write_word(child, PCI_EXP_LNKCTL, in pcie_aspm_configure_common_clock()
298 child_reg[PCI_FUNC(child->devfn)]); in pcie_aspm_configure_common_clock()
299 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg); in pcie_aspm_configure_common_clock()
316 return -1U; in calc_l0s_acceptable()
334 return -1U; in calc_l1_acceptable()
386 if ((endpoint->current_state != PCI_D0) && in pcie_aspm_check_latency()
387 (endpoint->current_state != PCI_UNKNOWN)) in pcie_aspm_check_latency()
390 link = endpoint->bus->self->link_state; in pcie_aspm_check_latency()
391 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; in pcie_aspm_check_latency()
395 if ((link->aspm_capable & ASPM_STATE_L0S_UP) && in pcie_aspm_check_latency()
396 (link->latency_up.l0s > acceptable->l0s)) in pcie_aspm_check_latency()
397 link->aspm_capable &= ~ASPM_STATE_L0S_UP; in pcie_aspm_check_latency()
400 if ((link->aspm_capable & ASPM_STATE_L0S_DW) && in pcie_aspm_check_latency()
401 (link->latency_dw.l0s > acceptable->l0s)) in pcie_aspm_check_latency()
402 link->aspm_capable &= ~ASPM_STATE_L0S_DW; in pcie_aspm_check_latency()
416 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1); in pcie_aspm_check_latency()
417 if ((link->aspm_capable & ASPM_STATE_L1) && in pcie_aspm_check_latency()
418 (latency + l1_switch_latency > acceptable->l1)) in pcie_aspm_check_latency()
419 link->aspm_capable &= ~ASPM_STATE_L1; in pcie_aspm_check_latency()
422 link = link->parent; in pcie_aspm_check_latency()
432 struct pci_dev *child; in pci_function_0() local
434 list_for_each_entry(child, &linkbus->devices, bus_list) in pci_function_0()
435 if (PCI_FUNC(child->devfn) == 0) in pci_function_0()
436 return child; in pci_function_0()
455 struct pci_dev *child = link->downstream, *parent = link->pdev; in aspm_calc_l1ss_info() local
462 if (!(link->aspm_support & ASPM_STATE_L1_2_MASK)) in aspm_calc_l1ss_info()
476 if (calc_l1ss_pwron(parent, scale1, val1) > in aspm_calc_l1ss_info()
477 calc_l1ss_pwron(child, scale2, val2)) { in aspm_calc_l1ss_info()
479 t_power_on = calc_l1ss_pwron(parent, scale1, val1); in aspm_calc_l1ss_info()
482 t_power_on = calc_l1ss_pwron(child, scale2, val2); in aspm_calc_l1ss_info()
491 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and in aspm_calc_l1ss_info()
492 * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at in aspm_calc_l1ss_info()
499 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1); in aspm_calc_l1ss_info()
500 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2); in aspm_calc_l1ss_info()
501 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1); in aspm_calc_l1ss_info()
502 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL2, &cctl2); in aspm_calc_l1ss_info()
513 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, in aspm_calc_l1ss_info()
515 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in aspm_calc_l1ss_info()
520 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2); in aspm_calc_l1ss_info()
521 pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2); in aspm_calc_l1ss_info()
524 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in aspm_calc_l1ss_info()
528 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in aspm_calc_l1ss_info()
531 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, in aspm_calc_l1ss_info()
536 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, 0, in aspm_calc_l1ss_info()
538 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, 0, in aspm_calc_l1ss_info()
545 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_aspm_cap_init() local
550 struct pci_bus *linkbus = parent->subordinate; in pcie_aspm_cap_init()
554 link->aspm_enabled = ASPM_STATE_ALL; in pcie_aspm_cap_init()
555 link->aspm_disable = ASPM_STATE_ALL; in pcie_aspm_cap_init()
563 pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap); in pcie_aspm_cap_init()
564 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap); in pcie_aspm_cap_init()
572 * Re-read upstream/downstream components' register state after in pcie_aspm_cap_init()
574 * read-only Link Capabilities may change depending on common clock in pcie_aspm_cap_init()
577 pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap); in pcie_aspm_cap_init()
578 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap); in pcie_aspm_cap_init()
579 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl); in pcie_aspm_cap_init()
580 pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl); in pcie_aspm_cap_init()
590 link->aspm_support |= ASPM_STATE_L0S; in pcie_aspm_cap_init()
593 link->aspm_enabled |= ASPM_STATE_L0S_UP; in pcie_aspm_cap_init()
595 link->aspm_enabled |= ASPM_STATE_L0S_DW; in pcie_aspm_cap_init()
596 link->latency_up.l0s = calc_l0s_latency(parent_lnkcap); in pcie_aspm_cap_init()
597 link->latency_dw.l0s = calc_l0s_latency(child_lnkcap); in pcie_aspm_cap_init()
601 link->aspm_support |= ASPM_STATE_L1; in pcie_aspm_cap_init()
604 link->aspm_enabled |= ASPM_STATE_L1; in pcie_aspm_cap_init()
605 link->latency_up.l1 = calc_l1_latency(parent_lnkcap); in pcie_aspm_cap_init()
606 link->latency_dw.l1 = calc_l1_latency(child_lnkcap); in pcie_aspm_cap_init()
609 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP, in pcie_aspm_cap_init()
611 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP, in pcie_aspm_cap_init()
624 if (!child->ltr_path) in pcie_aspm_cap_init()
628 link->aspm_support |= ASPM_STATE_L1_1; in pcie_aspm_cap_init()
630 link->aspm_support |= ASPM_STATE_L1_2; in pcie_aspm_cap_init()
632 link->aspm_support |= ASPM_STATE_L1_1_PCIPM; in pcie_aspm_cap_init()
634 link->aspm_support |= ASPM_STATE_L1_2_PCIPM; in pcie_aspm_cap_init()
637 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in pcie_aspm_cap_init()
640 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, in pcie_aspm_cap_init()
644 link->aspm_enabled |= ASPM_STATE_L1_1; in pcie_aspm_cap_init()
646 link->aspm_enabled |= ASPM_STATE_L1_2; in pcie_aspm_cap_init()
648 link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM; in pcie_aspm_cap_init()
650 link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM; in pcie_aspm_cap_init()
652 if (link->aspm_support & ASPM_STATE_L1SS) in pcie_aspm_cap_init()
656 link->aspm_default = link->aspm_enabled; in pcie_aspm_cap_init()
659 link->aspm_capable = link->aspm_support; in pcie_aspm_cap_init()
662 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_cap_init()
665 &link->acceptable[PCI_FUNC(child->devfn)]; in pcie_aspm_cap_init()
667 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT && in pcie_aspm_cap_init()
668 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END) in pcie_aspm_cap_init()
671 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); in pcie_aspm_cap_init()
674 acceptable->l0s = calc_l0s_acceptable(encoding); in pcie_aspm_cap_init()
677 acceptable->l1 = calc_l1_acceptable(encoding); in pcie_aspm_cap_init()
679 pcie_aspm_check_latency(child); in pcie_aspm_cap_init()
687 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_config_aspm_l1ss() local
689 enable_req = (link->aspm_enabled ^ state) & state; in pcie_config_aspm_l1ss()
693 * - When enabling L1.x, enable bit at parent first, then at child in pcie_config_aspm_l1ss()
694 * - When disabling L1.x, disable bit at child first, then at parent in pcie_config_aspm_l1ss()
695 * - When enabling ASPM L1.x, need to disable L1 in pcie_config_aspm_l1ss()
696 * (at child followed by parent). in pcie_config_aspm_l1ss()
697 * - The ASPM/PCIPM L1.2 must be disabled while programming timing in pcie_config_aspm_l1ss()
705 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
707 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
714 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL, in pcie_config_aspm_l1ss()
716 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL, in pcie_config_aspm_l1ss()
731 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
733 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
746 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_config_aspm_link() local
747 struct pci_bus *linkbus = parent->subordinate; in pcie_config_aspm_link()
750 state &= (link->aspm_capable & ~link->aspm_disable); in pcie_config_aspm_link()
757 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) { in pcie_config_aspm_link()
759 state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM); in pcie_config_aspm_link()
763 if (link->aspm_enabled == state) in pcie_config_aspm_link()
775 if (link->aspm_capable & ASPM_STATE_L1SS) in pcie_config_aspm_link()
785 pcie_config_aspm_dev(parent, upstream); in pcie_config_aspm_link()
786 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_config_aspm_link()
787 pcie_config_aspm_dev(child, dwstream); in pcie_config_aspm_link()
789 pcie_config_aspm_dev(parent, upstream); in pcie_config_aspm_link()
791 link->aspm_enabled = state; in pcie_config_aspm_link()
798 link = link->parent; in pcie_config_aspm_path()
804 link->pdev->link_state = NULL; in free_link_state()
810 struct pci_dev *child; in pcie_aspm_sanity_check() local
817 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { in pcie_aspm_sanity_check()
818 if (!pci_is_pcie(child)) in pcie_aspm_sanity_check()
819 return -EINVAL; in pcie_aspm_sanity_check()
824 * pre-1.1 device in pcie_aspm_sanity_check()
831 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use in pcie_aspm_sanity_check()
834 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); in pcie_aspm_sanity_check()
836 …pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\… in pcie_aspm_sanity_check()
837 return -EINVAL; in pcie_aspm_sanity_check()
851 INIT_LIST_HEAD(&link->sibling); in alloc_pcie_link_state()
852 link->pdev = pdev; in alloc_pcie_link_state()
853 link->downstream = pci_function_0(pdev->subordinate); in alloc_pcie_link_state()
856 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe in alloc_pcie_link_state()
864 !pdev->bus->parent->self) { in alloc_pcie_link_state()
865 link->root = link; in alloc_pcie_link_state()
867 struct pcie_link_state *parent; in alloc_pcie_link_state() local
869 parent = pdev->bus->parent->self->link_state; in alloc_pcie_link_state()
870 if (!parent) { in alloc_pcie_link_state()
875 link->parent = parent; in alloc_pcie_link_state()
876 link->root = link->parent->root; in alloc_pcie_link_state()
879 list_add(&link->sibling, &link_list); in alloc_pcie_link_state()
880 pdev->link_state = link; in alloc_pcie_link_state()
886 struct pci_dev *child; in pcie_aspm_update_sysfs_visibility() local
888 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) in pcie_aspm_update_sysfs_visibility()
889 sysfs_update_group(&child->dev.kobj, &aspm_ctrl_attr_group); in pcie_aspm_update_sysfs_visibility()
905 if (pdev->link_state) in pcie_aspm_init_link_state()
918 pdev->bus->self) in pcie_aspm_init_link_state()
922 if (list_empty(&pdev->subordinate->devices)) in pcie_aspm_init_link_state()
965 BUG_ON(root->parent); in pcie_update_aspm_capable()
967 if (link->root != root) in pcie_update_aspm_capable()
969 link->aspm_capable = link->aspm_support; in pcie_update_aspm_capable()
972 struct pci_dev *child; in pcie_update_aspm_capable() local
973 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_update_aspm_capable()
974 if (link->root != root) in pcie_update_aspm_capable()
976 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_update_aspm_capable()
977 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) && in pcie_update_aspm_capable()
978 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)) in pcie_update_aspm_capable()
980 pcie_aspm_check_latency(child); in pcie_update_aspm_capable()
988 struct pci_dev *parent = pdev->bus->self; in pcie_aspm_exit_link_state() local
991 if (!parent || !parent->link_state) in pcie_aspm_exit_link_state()
1000 if (!list_empty(&parent->subordinate->devices)) in pcie_aspm_exit_link_state()
1003 link = parent->link_state; in pcie_aspm_exit_link_state()
1004 root = link->root; in pcie_aspm_exit_link_state()
1005 parent_link = link->parent; in pcie_aspm_exit_link_state()
1009 list_del(&link->sibling); in pcie_aspm_exit_link_state()
1026 struct pcie_link_state *link = pdev->link_state; in pcie_aspm_pm_state_change()
1036 pcie_update_aspm_capable(link->root); in pcie_aspm_pm_state_change()
1044 struct pcie_link_state *link = pdev->link_state; in pcie_aspm_powersave_config_link()
1072 return bridge->link_state; in pcie_aspm_get_link()
1080 return -EINVAL; in __pci_disable_link_state()
1091 return -EPERM; in __pci_disable_link_state()
1098 link->aspm_disable |= ASPM_STATE_L0S; in __pci_disable_link_state()
1101 link->aspm_disable |= ASPM_STATE_L1 | ASPM_STATE_L1SS; in __pci_disable_link_state()
1103 link->aspm_disable |= ASPM_STATE_L1_1; in __pci_disable_link_state()
1105 link->aspm_disable |= ASPM_STATE_L1_2; in __pci_disable_link_state()
1107 link->aspm_disable |= ASPM_STATE_L1_1_PCIPM; in __pci_disable_link_state()
1109 link->aspm_disable |= ASPM_STATE_L1_2_PCIPM; in __pci_disable_link_state()
1113 link->clkpm_disable = 1; in __pci_disable_link_state()
1129 * pci_disable_link_state - Disable device's link state, so the link will
1150 return -EPERM; in pcie_aspm_set_policy()
1185 * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
1189 * is deallocated only when the last child of the bridge (i.e., @pdev or a
1200 return link->aspm_enabled; in pcie_aspm_enabled()
1211 return sprintf(buf, "%d\n", (link->aspm_enabled & state) ? 1 : 0); in aspm_attr_show_common()
1223 return -EINVAL; in aspm_attr_store_common()
1229 link->aspm_disable &= ~state; in aspm_attr_store_common()
1232 link->aspm_disable &= ~ASPM_STATE_L1; in aspm_attr_store_common()
1234 link->aspm_disable |= state; in aspm_attr_store_common()
1268 return sprintf(buf, "%d\n", link->clkpm_enabled); in ASPM_ATTR()
1280 return -EINVAL; in clkpm_store()
1285 link->clkpm_disable = !state_enable; in clkpm_store()
1332 return link->clkpm_capable ? a->mode : 0; in aspm_ctrl_attrs_are_visible()
1334 return link->aspm_capable & aspm_state_map[n - 1] ? a->mode : 0; in aspm_ctrl_attrs_are_visible()