145 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32);  in enable_ecrc_checking()
169 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32);  in disable_ecrc_checking()
258 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_clear_nonfatal_status()
259 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);  in pci_aer_clear_nonfatal_status()
277 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_clear_fatal_status()
278 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);  in pci_aer_clear_fatal_status()
304 		pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status);  in pci_aer_raw_clear_status()
308 	pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);  in pci_aer_raw_clear_status()
311 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_raw_clear_status()
339 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++);  in pci_save_aer_state()
340 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++);  in pci_save_aer_state()
341 	pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);  in pci_save_aer_state()
342 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++);  in pci_save_aer_state()
344 		pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++);  in pci_save_aer_state()
862 		pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);  in is_error_source()
863 		pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);  in is_error_source()
865 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in is_error_source()
866 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);  in is_error_source()
1049 		pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS,  in aer_get_device_error_info()
1051 		pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,  in aer_get_device_error_info()
1060 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,  in aer_get_device_error_info()
1062 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,  in aer_get_device_error_info()
1068 		pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp);  in aer_get_device_error_info()
1073 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1075 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1077 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1079 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1189 	pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status);  in aer_irq()
1193 	pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id);  in aer_irq()
1259 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_enable_rootport()
1261 	pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, &reg32);  in aer_enable_rootport()
1263 	pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, &reg32);  in aer_enable_rootport()
1273 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_enable_rootport()
1297 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_disable_rootport()
1302 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_disable_rootport()
1366 	pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_root_reset()
1374 	pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_root_reset()
1378 	pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_root_reset()