Lines Matching +full:cpu +full:- +full:viewed
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
34 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
175 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
176 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
177 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
294 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
302 return (log2_in - 12) + 0x1c; in brcm_pcie_encode_ibar_size()
305 return log2_in - 15; in brcm_pcie_encode_ibar_size()
338 return MDIO_RD_DONE(data) ? 0 : -EIO; in brcm_pcie_mdio_read()
359 return MDIO_WT_DONE(data) ? 0 : -EIO; in brcm_pcie_mdio_write()
372 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
377 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
384 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
390 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
398 return ssc && pll ? 0 : -EIO; in brcm_pcie_set_ssc()
404 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
405 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
408 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
411 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
424 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); in brcm_pcie_set_outbound_win()
425 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); in brcm_pcie_set_outbound_win()
429 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M; in brcm_pcie_set_outbound_win()
431 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
436 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
438 /* Write the cpu & limit addr upper bits */ in brcm_pcie_set_outbound_win()
443 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
446 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
449 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
452 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
478 dev = msi->dev; in brcm_pcie_msi_isr()
480 status = readl(msi->intr_base + MSI_INT_STATUS); in brcm_pcie_msi_isr()
481 status >>= msi->legacy_shift; in brcm_pcie_msi_isr()
483 for_each_set_bit(bit, &status, msi->nr) { in brcm_pcie_msi_isr()
484 virq = irq_find_mapping(msi->inner_domain, bit); in brcm_pcie_msi_isr()
498 msg->address_lo = lower_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
499 msg->address_hi = upper_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
500 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq; in brcm_msi_compose_msi_msg()
506 return -EINVAL; in brcm_msi_set_affinity()
512 const int shift_amt = data->hwirq + msi->legacy_shift; in brcm_msi_ack_irq()
514 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR); in brcm_msi_ack_irq()
529 mutex_lock(&msi->lock); in brcm_msi_alloc()
530 hwirq = bitmap_find_free_region(&msi->used, msi->nr, 0); in brcm_msi_alloc()
531 mutex_unlock(&msi->lock); in brcm_msi_alloc()
538 mutex_lock(&msi->lock); in brcm_msi_free()
539 bitmap_release_region(&msi->used, hwirq, 0); in brcm_msi_free()
540 mutex_unlock(&msi->lock); in brcm_msi_free()
546 struct brcm_msi *msi = domain->host_data; in brcm_irq_domain_alloc()
555 &brcm_msi_bottom_irq_chip, domain->host_data, in brcm_irq_domain_alloc()
566 brcm_msi_free(msi, d->hwirq); in brcm_irq_domain_free()
576 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np); in brcm_allocate_domains()
577 struct device *dev = msi->dev; in brcm_allocate_domains()
579 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi); in brcm_allocate_domains()
580 if (!msi->inner_domain) { in brcm_allocate_domains()
582 return -ENOMEM; in brcm_allocate_domains()
585 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in brcm_allocate_domains()
587 msi->inner_domain); in brcm_allocate_domains()
588 if (!msi->msi_domain) { in brcm_allocate_domains()
590 irq_domain_remove(msi->inner_domain); in brcm_allocate_domains()
591 return -ENOMEM; in brcm_allocate_domains()
599 irq_domain_remove(msi->msi_domain); in brcm_free_domains()
600 irq_domain_remove(msi->inner_domain); in brcm_free_domains()
605 struct brcm_msi *msi = pcie->msi; in brcm_msi_remove()
609 irq_set_chained_handler(msi->irq, NULL); in brcm_msi_remove()
610 irq_set_handler_data(msi->irq, NULL); in brcm_msi_remove()
616 u32 val = __GENMASK(31, msi->legacy_shift); in brcm_msi_set_regs()
618 writel(val, msi->intr_base + MSI_INT_MASK_CLR); in brcm_msi_set_regs()
619 writel(val, msi->intr_base + MSI_INT_CLR); in brcm_msi_set_regs()
625 writel(lower_32_bits(msi->target_addr) | 0x1, in brcm_msi_set_regs()
626 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO); in brcm_msi_set_regs()
627 writel(upper_32_bits(msi->target_addr), in brcm_msi_set_regs()
628 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI); in brcm_msi_set_regs()
630 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32; in brcm_msi_set_regs()
631 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG); in brcm_msi_set_regs()
638 struct device *dev = pcie->dev; in brcm_pcie_enable_msi()
640 irq = irq_of_parse_and_map(dev->of_node, 1); in brcm_pcie_enable_msi()
643 return -ENODEV; in brcm_pcie_enable_msi()
648 return -ENOMEM; in brcm_pcie_enable_msi()
650 mutex_init(&msi->lock); in brcm_pcie_enable_msi()
651 msi->dev = dev; in brcm_pcie_enable_msi()
652 msi->base = pcie->base; in brcm_pcie_enable_msi()
653 msi->np = pcie->np; in brcm_pcie_enable_msi()
654 msi->target_addr = pcie->msi_target_addr; in brcm_pcie_enable_msi()
655 msi->irq = irq; in brcm_pcie_enable_msi()
656 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; in brcm_pcie_enable_msi()
658 if (msi->legacy) { in brcm_pcie_enable_msi()
659 msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE; in brcm_pcie_enable_msi()
660 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR; in brcm_pcie_enable_msi()
661 msi->legacy_shift = 24; in brcm_pcie_enable_msi()
663 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE; in brcm_pcie_enable_msi()
664 msi->nr = BRCM_INT_PCI_MSI_NR; in brcm_pcie_enable_msi()
665 msi->legacy_shift = 0; in brcm_pcie_enable_msi()
672 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi); in brcm_pcie_enable_msi()
675 pcie->msi = msi; in brcm_pcie_enable_msi()
683 void __iomem *base = pcie->base; in brcm_pcie_rc_mode()
691 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); in brcm_pcie_link_up()
710 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_map_conf()
711 void __iomem *base = pcie->base; in brcm_pcie_map_conf()
719 idx = brcm_pcie_cfg_index(bus->number, devfn, 0); in brcm_pcie_map_conf()
720 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); in brcm_pcie_map_conf()
735 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
737 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
745 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
747 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
755 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
757 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
764 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
766 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
775 struct device *dev = pcie->dev; in brcm_pcie_get_rc_bar2_size_and_offset()
780 resource_list_for_each_entry(entry, &bridge->dma_ranges) { in brcm_pcie_get_rc_bar2_size_and_offset()
781 u64 pcie_beg = entry->res->start - entry->offset; in brcm_pcie_get_rc_bar2_size_and_offset()
783 size += entry->res->end - entry->res->start + 1; in brcm_pcie_get_rc_bar2_size_and_offset()
789 dev_err(dev, "DT node has no dma-ranges\n"); in brcm_pcie_get_rc_bar2_size_and_offset()
790 return -EINVAL; in brcm_pcie_get_rc_bar2_size_and_offset()
793 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, in brcm_pcie_get_rc_bar2_size_and_offset()
798 pcie->num_memc = 1; in brcm_pcie_get_rc_bar2_size_and_offset()
799 pcie->memc_size[0] = 1ULL << fls64(size - 1); in brcm_pcie_get_rc_bar2_size_and_offset()
801 pcie->num_memc = ret; in brcm_pcie_get_rc_bar2_size_and_offset()
804 /* Each memc is viewed through a "port" that is a power of 2 */ in brcm_pcie_get_rc_bar2_size_and_offset()
805 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_rc_bar2_size_and_offset()
806 size += pcie->memc_size[i]; in brcm_pcie_get_rc_bar2_size_and_offset()
808 /* System memory starts at this address in PCIe-space */ in brcm_pcie_get_rc_bar2_size_and_offset()
811 *rc_bar2_size = 1ULL << fls64(size - 1); in brcm_pcie_get_rc_bar2_size_and_offset()
815 * whatever the device-tree provides. This is because of an HW issue on in brcm_pcie_get_rc_bar2_size_and_offset()
817 * firmware has to dynamically edit dma-ranges due to a bug on the in brcm_pcie_get_rc_bar2_size_and_offset()
819 * lower 3GB of memory. Given this, we decided to keep the dma-ranges in brcm_pcie_get_rc_bar2_size_and_offset()
820 * in check, avoiding hard to debug device-tree related issues in the in brcm_pcie_get_rc_bar2_size_and_offset()
826 * matters, the viewport must start on a pcie-address that is aligned in brcm_pcie_get_rc_bar2_size_and_offset()
828 * represent system memory -- e.g. 3GB of memory requires a 4GB in brcm_pcie_get_rc_bar2_size_and_offset()
829 * viewport -- we can map the outbound memory in or after 3GB and even in brcm_pcie_get_rc_bar2_size_and_offset()
836 * - The best-case scenario, memory up to 3GB, is to place the inbound in brcm_pcie_get_rc_bar2_size_and_offset()
837 * region in the first 4GB of pcie-space, as some legacy devices can in brcm_pcie_get_rc_bar2_size_and_offset()
841 * - If the system memory is 4GB or larger we cannot start the inbound in brcm_pcie_get_rc_bar2_size_and_offset()
846 if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) || in brcm_pcie_get_rc_bar2_size_and_offset()
850 return -EINVAL; in brcm_pcie_get_rc_bar2_size_and_offset()
860 void __iomem *base = pcie->base; in brcm_pcie_setup()
861 struct device *dev = pcie->dev; in brcm_pcie_setup()
871 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_setup()
875 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
888 if (pcie->type == BCM2711) in brcm_pcie_setup()
890 else if (pcie->type == BCM7278) in brcm_pcie_setup()
914 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
915 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; in brcm_pcie_setup()
931 * account the rounding-up we're forced to perform). in brcm_pcie_setup()
934 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; in brcm_pcie_setup()
936 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; in brcm_pcie_setup()
938 /* disable the PCIe->GISB memory window (RC_BAR1) */ in brcm_pcie_setup()
943 /* disable the PCIe->SCB memory window (RC_BAR3) */ in brcm_pcie_setup()
948 if (pcie->gen) in brcm_pcie_setup()
949 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_setup()
952 pcie->perst_set(pcie, 0); in brcm_pcie_setup()
956 * Intermittently check status for link-up, up to a total of 100ms. in brcm_pcie_setup()
963 return -ENODEV; in brcm_pcie_setup()
968 return -EINVAL; in brcm_pcie_setup()
971 resource_list_for_each_entry(entry, &bridge->windows) { in brcm_pcie_setup()
972 res = entry->res; in brcm_pcie_setup()
978 dev_err(pcie->dev, "too many outbound wins\n"); in brcm_pcie_setup()
979 return -EINVAL; in brcm_pcie_setup()
982 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, in brcm_pcie_setup()
983 res->start - entry->offset, in brcm_pcie_setup()
988 /* Don't advertise L0s capability if 'aspm-no-l0s' */ in brcm_pcie_setup()
990 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
999 * a PCIe-PCIe bridge (the default setting is to be EP mode). in brcm_pcie_setup()
1006 if (pcie->ssc) { in brcm_pcie_setup()
1021 /* PCIe->SCB endian mode for BAR */ in brcm_pcie_setup()
1038 /* L23 is a low-power PCIe link state */
1041 void __iomem *base = pcie->base; in brcm_pcie_enter_l23()
1061 dev_err(pcie->dev, "failed to enter low-power link state\n"); in brcm_pcie_enter_l23()
1074 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1; in brcm_phy_cntl()
1075 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1; in brcm_phy_cntl()
1078 void __iomem *base = pcie->base; in brcm_phy_cntl()
1081 for (i = beg; i != end; start ? i++ : i--) { in brcm_phy_cntl()
1093 ret = (tmp & combined_mask) == val ? 0 : -EIO; in brcm_phy_cntl()
1095 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); in brcm_phy_cntl()
1102 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1107 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1112 void __iomem *base = pcie->base; in brcm_pcie_turn_off()
1118 pcie->perst_set(pcie, 1); in brcm_pcie_turn_off()
1131 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_turn_off()
1141 clk_disable_unprepare(pcie->clk); in brcm_pcie_suspend()
1153 base = pcie->base; in brcm_pcie_resume()
1154 clk_prepare_enable(pcie->clk); in brcm_pcie_resume()
1161 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume()
1175 if (pcie->msi) in brcm_pcie_resume()
1176 brcm_msi_set_regs(pcie->msi); in brcm_pcie_resume()
1181 clk_disable_unprepare(pcie->clk); in brcm_pcie_resume()
1190 reset_control_assert(pcie->rescal); in __brcm_pcie_remove()
1191 clk_disable_unprepare(pcie->clk); in __brcm_pcie_remove()
1199 pci_stop_root_bus(bridge->bus); in brcm_pcie_remove()
1200 pci_remove_root_bus(bridge->bus); in brcm_pcie_remove()
1207 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1208 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1209 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1210 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1211 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1217 struct device_node *np = pdev->dev.of_node, *msi_np; in brcm_pcie_probe()
1223 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); in brcm_pcie_probe()
1225 return -ENOMEM; in brcm_pcie_probe()
1227 data = of_device_get_match_data(&pdev->dev); in brcm_pcie_probe()
1230 return -EINVAL; in brcm_pcie_probe()
1234 pcie->dev = &pdev->dev; in brcm_pcie_probe()
1235 pcie->np = np; in brcm_pcie_probe()
1236 pcie->reg_offsets = data->offsets; in brcm_pcie_probe()
1237 pcie->type = data->type; in brcm_pcie_probe()
1238 pcie->perst_set = data->perst_set; in brcm_pcie_probe()
1239 pcie->bridge_sw_init_set = data->bridge_sw_init_set; in brcm_pcie_probe()
1241 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1242 if (IS_ERR(pcie->base)) in brcm_pcie_probe()
1243 return PTR_ERR(pcie->base); in brcm_pcie_probe()
1245 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); in brcm_pcie_probe()
1246 if (IS_ERR(pcie->clk)) in brcm_pcie_probe()
1247 return PTR_ERR(pcie->clk); in brcm_pcie_probe()
1250 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1252 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
1254 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_probe()
1256 dev_err(&pdev->dev, "could not enable clock\n"); in brcm_pcie_probe()
1259 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); in brcm_pcie_probe()
1260 if (IS_ERR(pcie->rescal)) { in brcm_pcie_probe()
1261 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1262 return PTR_ERR(pcie->rescal); in brcm_pcie_probe()
1265 ret = reset_control_deassert(pcie->rescal); in brcm_pcie_probe()
1267 dev_err(&pdev->dev, "failed to deassert 'rescal'\n"); in brcm_pcie_probe()
1271 reset_control_assert(pcie->rescal); in brcm_pcie_probe()
1272 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1280 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); in brcm_pcie_probe()
1282 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1283 if (pci_msi_enabled() && msi_np == pcie->np) { in brcm_pcie_probe()
1286 dev_err(pcie->dev, "probe of internal MSI failed"); in brcm_pcie_probe()
1291 bridge->ops = &brcm_pcie_ops; in brcm_pcie_probe()
1292 bridge->sysdata = pcie; in brcm_pcie_probe()
1313 .name = "brcm-pcie",