Lines Matching +full:tegra210 +full:- +full:pmc
1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
43 #include <soc/tegra/pmc.h>
270 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
397 writel(value, pcie->afi + offset); in afi_writel()
402 return readl(pcie->afi + offset); in afi_readl()
408 writel(value, pcie->pads + offset); in pads_writel()
413 return readl(pcie->pads + offset); in pads_readl()
448 struct tegra_pcie *pcie = bus->sysdata; in tegra_pcie_map_bus()
451 if (bus->number == 0) { in tegra_pcie_map_bus()
455 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_map_bus()
456 if (port->index + 1 == slot) { in tegra_pcie_map_bus()
457 addr = port->base + (where & ~3); in tegra_pcie_map_bus()
465 offset = tegra_pcie_conf_offset(bus->number, devfn, where); in tegra_pcie_map_bus()
468 base = 0xfe100000 + ((offset & ~(SZ_4K - 1)) >> 8); in tegra_pcie_map_bus()
472 addr = pcie->cfg + (offset & (SZ_4K - 1)); in tegra_pcie_map_bus()
481 if (bus->number == 0) in tegra_pcie_config_read()
491 if (bus->number == 0) in tegra_pcie_config_write()
506 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_port_get_pex_ctrl()
509 switch (port->index) { in tegra_pcie_port_get_pex_ctrl()
519 ret = soc->afi_pex2_ctrl; in tegra_pcie_port_get_pex_ctrl()
532 if (port->reset_gpio) { in tegra_pcie_port_reset()
533 gpiod_set_value(port->reset_gpio, 1); in tegra_pcie_port_reset()
535 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_reset()
537 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_reset()
542 if (port->reset_gpio) { in tegra_pcie_port_reset()
543 gpiod_set_value(port->reset_gpio, 0); in tegra_pcie_port_reset()
545 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_reset()
547 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_reset()
553 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_enable_rp_features()
557 value = readl(port->base + RP_VEND_CTL1); in tegra_pcie_enable_rp_features()
559 writel(value, port->base + RP_VEND_CTL1); in tegra_pcie_enable_rp_features()
562 value = readl(port->base + RP_VEND_XP); in tegra_pcie_enable_rp_features()
565 writel(value, port->base + RP_VEND_XP); in tegra_pcie_enable_rp_features()
571 value = readl(port->base + RP_VEND_XP_BIST); in tegra_pcie_enable_rp_features()
573 writel(value, port->base + RP_VEND_XP_BIST); in tegra_pcie_enable_rp_features()
575 value = readl(port->base + RP_PRIV_MISC); in tegra_pcie_enable_rp_features()
579 if (soc->update_clamp_threshold) { in tegra_pcie_enable_rp_features()
586 writel(value, port->base + RP_PRIV_MISC); in tegra_pcie_enable_rp_features()
591 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_program_ectl_settings()
594 value = readl(port->base + RP_ECTL_2_R1); in tegra_pcie_program_ectl_settings()
596 value |= soc->ectl.regs.rp_ectl_2_r1; in tegra_pcie_program_ectl_settings()
597 writel(value, port->base + RP_ECTL_2_R1); in tegra_pcie_program_ectl_settings()
599 value = readl(port->base + RP_ECTL_4_R1); in tegra_pcie_program_ectl_settings()
601 value |= soc->ectl.regs.rp_ectl_4_r1 << in tegra_pcie_program_ectl_settings()
603 writel(value, port->base + RP_ECTL_4_R1); in tegra_pcie_program_ectl_settings()
605 value = readl(port->base + RP_ECTL_5_R1); in tegra_pcie_program_ectl_settings()
607 value |= soc->ectl.regs.rp_ectl_5_r1; in tegra_pcie_program_ectl_settings()
608 writel(value, port->base + RP_ECTL_5_R1); in tegra_pcie_program_ectl_settings()
610 value = readl(port->base + RP_ECTL_6_R1); in tegra_pcie_program_ectl_settings()
612 value |= soc->ectl.regs.rp_ectl_6_r1; in tegra_pcie_program_ectl_settings()
613 writel(value, port->base + RP_ECTL_6_R1); in tegra_pcie_program_ectl_settings()
615 value = readl(port->base + RP_ECTL_2_R2); in tegra_pcie_program_ectl_settings()
617 value |= soc->ectl.regs.rp_ectl_2_r2; in tegra_pcie_program_ectl_settings()
618 writel(value, port->base + RP_ECTL_2_R2); in tegra_pcie_program_ectl_settings()
620 value = readl(port->base + RP_ECTL_4_R2); in tegra_pcie_program_ectl_settings()
622 value |= soc->ectl.regs.rp_ectl_4_r2 << in tegra_pcie_program_ectl_settings()
624 writel(value, port->base + RP_ECTL_4_R2); in tegra_pcie_program_ectl_settings()
626 value = readl(port->base + RP_ECTL_5_R2); in tegra_pcie_program_ectl_settings()
628 value |= soc->ectl.regs.rp_ectl_5_r2; in tegra_pcie_program_ectl_settings()
629 writel(value, port->base + RP_ECTL_5_R2); in tegra_pcie_program_ectl_settings()
631 value = readl(port->base + RP_ECTL_6_R2); in tegra_pcie_program_ectl_settings()
633 value |= soc->ectl.regs.rp_ectl_6_r2; in tegra_pcie_program_ectl_settings()
634 writel(value, port->base + RP_ECTL_6_R2); in tegra_pcie_program_ectl_settings()
639 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_apply_sw_fixup()
644 * instability in deskew logic on lane-0. Increase the deskew in tegra_pcie_apply_sw_fixup()
647 if (soc->program_deskew_time) { in tegra_pcie_apply_sw_fixup()
648 value = readl(port->base + RP_VEND_CTL0); in tegra_pcie_apply_sw_fixup()
651 writel(value, port->base + RP_VEND_CTL0); in tegra_pcie_apply_sw_fixup()
654 if (soc->update_fc_timer) { in tegra_pcie_apply_sw_fixup()
655 value = readl(port->base + RP_VEND_XP); in tegra_pcie_apply_sw_fixup()
657 value |= soc->update_fc_threshold; in tegra_pcie_apply_sw_fixup()
658 writel(value, port->base + RP_VEND_XP); in tegra_pcie_apply_sw_fixup()
663 * root port advertises both Gen-1 and Gen-2 speeds in Tegra. in tegra_pcie_apply_sw_fixup()
665 * only Gen-1 and after link is up, retrain link to Gen-2 speed in tegra_pcie_apply_sw_fixup()
667 value = readl(port->base + RP_LINK_CONTROL_STATUS_2); in tegra_pcie_apply_sw_fixup()
670 writel(value, port->base + RP_LINK_CONTROL_STATUS_2); in tegra_pcie_apply_sw_fixup()
676 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_port_enable()
680 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_enable()
683 if (soc->has_pex_clkreq_en) in tegra_pcie_port_enable()
688 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_enable()
692 if (soc->force_pca_enable) { in tegra_pcie_port_enable()
693 value = readl(port->base + RP_VEND_CTL2); in tegra_pcie_port_enable()
695 writel(value, port->base + RP_VEND_CTL2); in tegra_pcie_port_enable()
700 if (soc->ectl.enable) in tegra_pcie_port_enable()
709 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_port_disable()
713 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_disable()
715 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_disable()
718 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_disable()
720 if (soc->has_pex_clkreq_en) in tegra_pcie_port_disable()
724 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_disable()
727 value = afi_readl(port->pcie, AFI_PCIE_CONFIG); in tegra_pcie_port_disable()
728 value |= AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); in tegra_pcie_port_disable()
729 value |= AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(port->index); in tegra_pcie_port_disable()
730 afi_writel(port->pcie, value, AFI_PCIE_CONFIG); in tegra_pcie_port_disable()
735 struct tegra_pcie *pcie = port->pcie; in tegra_pcie_port_free()
736 struct device *dev = pcie->dev; in tegra_pcie_port_free()
738 devm_iounmap(dev, port->base); in tegra_pcie_port_free()
739 devm_release_mem_region(dev, port->regs.start, in tegra_pcie_port_free()
740 resource_size(&port->regs)); in tegra_pcie_port_free()
741 list_del(&port->list); in tegra_pcie_port_free()
748 dev->class = PCI_CLASS_BRIDGE_PCI << 8; in tegra_pcie_fixup_class()
767 struct tegra_pcie *pcie = pdev->bus->sysdata; in tegra_pcie_map_irq()
774 irq = pcie->irq; in tegra_pcie_map_irq()
799 struct device *dev = pcie->dev; in tegra_pcie_isr()
837 * - 0xfdfc000000: I/O space
838 * - 0xfdfe000000: type 0 configuration space
839 * - 0xfdff000000: type 1 configuration space
840 * - 0xfe00000000: type 0 extended configuration space
841 * - 0xfe10000000: type 1 extended configuration space
850 size = resource_size(&pcie->cs); in tegra_pcie_setup_translations()
851 afi_writel(pcie, pcie->cs.start, AFI_AXI_BAR0_START); in tegra_pcie_setup_translations()
854 resource_list_for_each_entry(entry, &bridge->windows) { in tegra_pcie_setup_translations()
856 struct resource *res = entry->res; in tegra_pcie_setup_translations()
864 axi_address = pci_pio_to_address(res->start); in tegra_pcie_setup_translations()
870 fpci_bar = (((res->start >> 12) & 0x0fffffff) << 4) | 0x1; in tegra_pcie_setup_translations()
871 axi_address = res->start; in tegra_pcie_setup_translations()
873 if (res->flags & IORESOURCE_PREFETCH) { in tegra_pcie_setup_translations()
898 if (pcie->soc->has_cache_bars) { in tegra_pcie_setup_translations()
915 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_pll_wait()
921 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_pll_wait()
926 return -ETIMEDOUT; in tegra_pcie_pll_wait()
931 struct device *dev = pcie->dev; in tegra_pcie_phy_enable()
932 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_phy_enable()
948 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
950 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; in tegra_pcie_phy_enable()
951 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
954 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
956 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
961 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
963 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
987 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_phy_disable()
1001 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_disable()
1003 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_disable()
1012 struct device *dev = port->pcie->dev; in tegra_pcie_port_phy_power_on()
1016 for (i = 0; i < port->lanes; i++) { in tegra_pcie_port_phy_power_on()
1017 err = phy_power_on(port->phys[i]); in tegra_pcie_port_phy_power_on()
1029 struct device *dev = port->pcie->dev; in tegra_pcie_port_phy_power_off()
1033 for (i = 0; i < port->lanes; i++) { in tegra_pcie_port_phy_power_off()
1034 err = phy_power_off(port->phys[i]); in tegra_pcie_port_phy_power_off()
1047 struct device *dev = pcie->dev; in tegra_pcie_phy_power_on()
1051 if (pcie->legacy_phy) { in tegra_pcie_phy_power_on()
1052 if (pcie->phy) in tegra_pcie_phy_power_on()
1053 err = phy_power_on(pcie->phy); in tegra_pcie_phy_power_on()
1063 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_phy_power_on()
1068 port->index, err); in tegra_pcie_phy_power_on()
1078 struct device *dev = pcie->dev; in tegra_pcie_phy_power_off()
1082 if (pcie->legacy_phy) { in tegra_pcie_phy_power_off()
1083 if (pcie->phy) in tegra_pcie_phy_power_off()
1084 err = phy_power_off(pcie->phy); in tegra_pcie_phy_power_off()
1094 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_phy_power_off()
1099 port->index, err); in tegra_pcie_phy_power_off()
1109 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_enable_controller()
1114 if (pcie->phy) { in tegra_pcie_enable_controller()
1122 if (soc->has_pex_bias_ctrl) in tegra_pcie_enable_controller()
1128 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config; in tegra_pcie_enable_controller()
1131 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_enable_controller()
1132 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); in tegra_pcie_enable_controller()
1133 value &= ~AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(port->index); in tegra_pcie_enable_controller()
1138 if (soc->has_gen2) { in tegra_pcie_enable_controller()
1158 if (soc->has_intr_prsnt_sense) in tegra_pcie_enable_controller()
1173 struct device *dev = pcie->dev; in tegra_pcie_power_off()
1174 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_power_off()
1177 reset_control_assert(pcie->afi_rst); in tegra_pcie_power_off()
1179 clk_disable_unprepare(pcie->pll_e); in tegra_pcie_power_off()
1180 if (soc->has_cml_clk) in tegra_pcie_power_off()
1181 clk_disable_unprepare(pcie->cml_clk); in tegra_pcie_power_off()
1182 clk_disable_unprepare(pcie->afi_clk); in tegra_pcie_power_off()
1184 if (!dev->pm_domain) in tegra_pcie_power_off()
1187 err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies); in tegra_pcie_power_off()
1194 struct device *dev = pcie->dev; in tegra_pcie_power_on()
1195 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_power_on()
1198 reset_control_assert(pcie->pcie_xrst); in tegra_pcie_power_on()
1199 reset_control_assert(pcie->afi_rst); in tegra_pcie_power_on()
1200 reset_control_assert(pcie->pex_rst); in tegra_pcie_power_on()
1202 if (!dev->pm_domain) in tegra_pcie_power_on()
1206 err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies); in tegra_pcie_power_on()
1210 if (!dev->pm_domain) { in tegra_pcie_power_on()
1223 err = clk_prepare_enable(pcie->afi_clk); in tegra_pcie_power_on()
1229 if (soc->has_cml_clk) { in tegra_pcie_power_on()
1230 err = clk_prepare_enable(pcie->cml_clk); in tegra_pcie_power_on()
1237 err = clk_prepare_enable(pcie->pll_e); in tegra_pcie_power_on()
1243 reset_control_deassert(pcie->afi_rst); in tegra_pcie_power_on()
1248 if (soc->has_cml_clk) in tegra_pcie_power_on()
1249 clk_disable_unprepare(pcie->cml_clk); in tegra_pcie_power_on()
1251 clk_disable_unprepare(pcie->afi_clk); in tegra_pcie_power_on()
1253 if (!dev->pm_domain) in tegra_pcie_power_on()
1256 regulator_bulk_disable(pcie->num_supplies, pcie->supplies); in tegra_pcie_power_on()
1263 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_apply_pad_settings()
1266 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0); in tegra_pcie_apply_pad_settings()
1268 if (soc->num_ports > 2) in tegra_pcie_apply_pad_settings()
1269 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); in tegra_pcie_apply_pad_settings()
1274 struct device *dev = pcie->dev; in tegra_pcie_clocks_get()
1275 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_clocks_get()
1277 pcie->pex_clk = devm_clk_get(dev, "pex"); in tegra_pcie_clocks_get()
1278 if (IS_ERR(pcie->pex_clk)) in tegra_pcie_clocks_get()
1279 return PTR_ERR(pcie->pex_clk); in tegra_pcie_clocks_get()
1281 pcie->afi_clk = devm_clk_get(dev, "afi"); in tegra_pcie_clocks_get()
1282 if (IS_ERR(pcie->afi_clk)) in tegra_pcie_clocks_get()
1283 return PTR_ERR(pcie->afi_clk); in tegra_pcie_clocks_get()
1285 pcie->pll_e = devm_clk_get(dev, "pll_e"); in tegra_pcie_clocks_get()
1286 if (IS_ERR(pcie->pll_e)) in tegra_pcie_clocks_get()
1287 return PTR_ERR(pcie->pll_e); in tegra_pcie_clocks_get()
1289 if (soc->has_cml_clk) { in tegra_pcie_clocks_get()
1290 pcie->cml_clk = devm_clk_get(dev, "cml"); in tegra_pcie_clocks_get()
1291 if (IS_ERR(pcie->cml_clk)) in tegra_pcie_clocks_get()
1292 return PTR_ERR(pcie->cml_clk); in tegra_pcie_clocks_get()
1300 struct device *dev = pcie->dev; in tegra_pcie_resets_get()
1302 pcie->pex_rst = devm_reset_control_get_exclusive(dev, "pex"); in tegra_pcie_resets_get()
1303 if (IS_ERR(pcie->pex_rst)) in tegra_pcie_resets_get()
1304 return PTR_ERR(pcie->pex_rst); in tegra_pcie_resets_get()
1306 pcie->afi_rst = devm_reset_control_get_exclusive(dev, "afi"); in tegra_pcie_resets_get()
1307 if (IS_ERR(pcie->afi_rst)) in tegra_pcie_resets_get()
1308 return PTR_ERR(pcie->afi_rst); in tegra_pcie_resets_get()
1310 pcie->pcie_xrst = devm_reset_control_get_exclusive(dev, "pcie_x"); in tegra_pcie_resets_get()
1311 if (IS_ERR(pcie->pcie_xrst)) in tegra_pcie_resets_get()
1312 return PTR_ERR(pcie->pcie_xrst); in tegra_pcie_resets_get()
1319 struct device *dev = pcie->dev; in tegra_pcie_phys_get_legacy()
1322 pcie->phy = devm_phy_optional_get(dev, "pcie"); in tegra_pcie_phys_get_legacy()
1323 if (IS_ERR(pcie->phy)) { in tegra_pcie_phys_get_legacy()
1324 err = PTR_ERR(pcie->phy); in tegra_pcie_phys_get_legacy()
1329 err = phy_init(pcie->phy); in tegra_pcie_phys_get_legacy()
1335 pcie->legacy_phy = true; in tegra_pcie_phys_get_legacy()
1348 name = kasprintf(GFP_KERNEL, "%s-%u", consumer, index); in devm_of_phy_optional_get_index()
1350 return ERR_PTR(-ENOMEM); in devm_of_phy_optional_get_index()
1355 if (PTR_ERR(phy) == -ENODEV) in devm_of_phy_optional_get_index()
1363 struct device *dev = port->pcie->dev; in tegra_pcie_port_get_phys()
1368 port->phys = devm_kcalloc(dev, sizeof(phy), port->lanes, GFP_KERNEL); in tegra_pcie_port_get_phys()
1369 if (!port->phys) in tegra_pcie_port_get_phys()
1370 return -ENOMEM; in tegra_pcie_port_get_phys()
1372 for (i = 0; i < port->lanes; i++) { in tegra_pcie_port_get_phys()
1373 phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i); in tegra_pcie_port_get_phys()
1387 port->phys[i] = phy; in tegra_pcie_port_get_phys()
1395 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_phys_get()
1396 struct device_node *np = pcie->dev->of_node; in tegra_pcie_phys_get()
1400 if (!soc->has_gen2 || of_find_property(np, "phys", NULL) != NULL) in tegra_pcie_phys_get()
1403 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_phys_get()
1415 struct device *dev = pcie->dev; in tegra_pcie_phys_put()
1418 if (pcie->legacy_phy) { in tegra_pcie_phys_put()
1419 err = phy_exit(pcie->phy); in tegra_pcie_phys_put()
1425 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_phys_put()
1426 for (i = 0; i < port->lanes; i++) { in tegra_pcie_phys_put()
1427 err = phy_exit(port->phys[i]); in tegra_pcie_phys_put()
1438 struct device *dev = pcie->dev; in tegra_pcie_get_resources()
1441 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_get_resources()
1456 if (soc->program_uphy) { in tegra_pcie_get_resources()
1464 pcie->pads = devm_platform_ioremap_resource_byname(pdev, "pads"); in tegra_pcie_get_resources()
1465 if (IS_ERR(pcie->pads)) { in tegra_pcie_get_resources()
1466 err = PTR_ERR(pcie->pads); in tegra_pcie_get_resources()
1470 pcie->afi = devm_platform_ioremap_resource_byname(pdev, "afi"); in tegra_pcie_get_resources()
1471 if (IS_ERR(pcie->afi)) { in tegra_pcie_get_resources()
1472 err = PTR_ERR(pcie->afi); in tegra_pcie_get_resources()
1479 err = -EADDRNOTAVAIL; in tegra_pcie_get_resources()
1483 pcie->cs = *res; in tegra_pcie_get_resources()
1486 pcie->cs.end = pcie->cs.start + SZ_4K - 1; in tegra_pcie_get_resources()
1488 pcie->cfg = devm_ioremap_resource(dev, &pcie->cs); in tegra_pcie_get_resources()
1489 if (IS_ERR(pcie->cfg)) { in tegra_pcie_get_resources()
1490 err = PTR_ERR(pcie->cfg); in tegra_pcie_get_resources()
1499 pcie->irq = err; in tegra_pcie_get_resources()
1501 err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie); in tegra_pcie_get_resources()
1510 if (soc->program_uphy) in tegra_pcie_get_resources()
1517 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_put_resources()
1519 if (pcie->irq > 0) in tegra_pcie_put_resources()
1520 free_irq(pcie->irq, pcie); in tegra_pcie_put_resources()
1522 if (soc->program_uphy) in tegra_pcie_put_resources()
1530 struct tegra_pcie *pcie = port->pcie; in tegra_pcie_pme_turnoff()
1531 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_pme_turnoff()
1537 val |= (0x1 << soc->ports[port->index].pme.turnoff_bit); in tegra_pcie_pme_turnoff()
1540 ack_bit = soc->ports[port->index].pme.ack_bit; in tegra_pcie_pme_turnoff()
1541 err = readl_poll_timeout(pcie->afi + AFI_PCIE_PME, val, in tegra_pcie_pme_turnoff()
1544 dev_err(pcie->dev, "PME Ack is not received on port: %d\n", in tegra_pcie_pme_turnoff()
1545 port->index); in tegra_pcie_pme_turnoff()
1550 val &= ~(0x1 << soc->ports[port->index].pme.turnoff_bit); in tegra_pcie_pme_turnoff()
1558 mutex_lock(&chip->lock); in tegra_msi_alloc()
1560 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR); in tegra_msi_alloc()
1562 set_bit(msi, chip->used); in tegra_msi_alloc()
1564 msi = -ENOSPC; in tegra_msi_alloc()
1566 mutex_unlock(&chip->lock); in tegra_msi_alloc()
1573 struct device *dev = chip->chip.dev; in tegra_msi_free()
1575 mutex_lock(&chip->lock); in tegra_msi_free()
1577 if (!test_bit(irq, chip->used)) in tegra_msi_free()
1580 clear_bit(irq, chip->used); in tegra_msi_free()
1582 mutex_unlock(&chip->lock); in tegra_msi_free()
1588 struct device *dev = pcie->dev; in tegra_pcie_msi_irq()
1589 struct tegra_msi *msi = &pcie->msi; in tegra_pcie_msi_irq()
1603 irq = irq_find_mapping(msi->domain, index); in tegra_pcie_msi_irq()
1605 if (test_bit(index, msi->used)) in tegra_pcie_msi_irq()
1639 irq = irq_create_mapping(msi->domain, hwirq); in tegra_msi_setup_irq()
1642 return -EINVAL; in tegra_msi_setup_irq()
1647 msg.address_lo = lower_32_bits(msi->phys); in tegra_msi_setup_irq()
1648 msg.address_hi = upper_32_bits(msi->phys); in tegra_msi_setup_irq()
1679 irq_set_chip_data(irq, domain->host_data); in tegra_msi_map()
1693 struct platform_device *pdev = to_platform_device(pcie->dev); in tegra_pcie_msi_setup()
1694 struct tegra_msi *msi = &pcie->msi; in tegra_pcie_msi_setup()
1695 struct device *dev = pcie->dev; in tegra_pcie_msi_setup()
1698 mutex_init(&msi->lock); in tegra_pcie_msi_setup()
1700 msi->chip.dev = dev; in tegra_pcie_msi_setup()
1701 msi->chip.setup_irq = tegra_msi_setup_irq; in tegra_pcie_msi_setup()
1702 msi->chip.teardown_irq = tegra_msi_teardown_irq; in tegra_pcie_msi_setup()
1704 msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR, in tegra_pcie_msi_setup()
1705 &msi_domain_ops, &msi->chip); in tegra_pcie_msi_setup()
1706 if (!msi->domain) { in tegra_pcie_msi_setup()
1708 return -ENOMEM; in tegra_pcie_msi_setup()
1715 msi->irq = err; in tegra_pcie_msi_setup()
1717 err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD, in tegra_pcie_msi_setup()
1724 /* Though the PCIe controller can address >32-bit address space, to in tegra_pcie_msi_setup()
1725 * facilitate endpoints that support only 32-bit MSI target address, in tegra_pcie_msi_setup()
1726 * the mask is set to 32-bit to make sure that MSI target address is in tegra_pcie_msi_setup()
1727 * always a 32-bit address in tegra_pcie_msi_setup()
1735 msi->virt = dma_alloc_attrs(dev, PAGE_SIZE, &msi->phys, GFP_KERNEL, in tegra_pcie_msi_setup()
1737 if (!msi->virt) { in tegra_pcie_msi_setup()
1739 err = -ENOMEM; in tegra_pcie_msi_setup()
1743 host->msi = &msi->chip; in tegra_pcie_msi_setup()
1748 free_irq(msi->irq, pcie); in tegra_pcie_msi_setup()
1750 irq_domain_remove(msi->domain); in tegra_pcie_msi_setup()
1756 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_enable_msi()
1757 struct tegra_msi *msi = &pcie->msi; in tegra_pcie_enable_msi()
1760 afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST); in tegra_pcie_enable_msi()
1761 afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST); in tegra_pcie_enable_msi()
1783 struct tegra_msi *msi = &pcie->msi; in tegra_pcie_msi_teardown()
1786 dma_free_attrs(pcie->dev, PAGE_SIZE, msi->virt, msi->phys, in tegra_pcie_msi_teardown()
1789 if (msi->irq > 0) in tegra_pcie_msi_teardown()
1790 free_irq(msi->irq, pcie); in tegra_pcie_msi_teardown()
1793 irq = irq_find_mapping(msi->domain, i); in tegra_pcie_msi_teardown()
1798 irq_domain_remove(msi->domain); in tegra_pcie_msi_teardown()
1835 struct device *dev = pcie->dev; in tegra_pcie_get_xbar_config()
1836 struct device_node *np = dev->of_node; in tegra_pcie_get_xbar_config()
1838 if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) { in tegra_pcie_get_xbar_config()
1862 } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie") || in tegra_pcie_get_xbar_config()
1863 of_device_is_compatible(np, "nvidia,tegra210-pcie")) { in tegra_pcie_get_xbar_config()
1875 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { in tegra_pcie_get_xbar_config()
1892 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { in tegra_pcie_get_xbar_config()
1895 dev_info(dev, "single-mode configuration\n"); in tegra_pcie_get_xbar_config()
1900 dev_info(dev, "dual-mode configuration\n"); in tegra_pcie_get_xbar_config()
1906 return -EINVAL; in tegra_pcie_get_xbar_config()
1922 snprintf(property, 32, "%s-supply", supplies[i].supply); in of_regulator_bulk_available()
1934 * number of cases but is not future proof. However to preserve backwards-
1940 struct device *dev = pcie->dev; in tegra_pcie_get_legacy_regulators()
1941 struct device_node *np = dev->of_node; in tegra_pcie_get_legacy_regulators()
1943 if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) in tegra_pcie_get_legacy_regulators()
1944 pcie->num_supplies = 3; in tegra_pcie_get_legacy_regulators()
1945 else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) in tegra_pcie_get_legacy_regulators()
1946 pcie->num_supplies = 2; in tegra_pcie_get_legacy_regulators()
1948 if (pcie->num_supplies == 0) { in tegra_pcie_get_legacy_regulators()
1950 return -ENODEV; in tegra_pcie_get_legacy_regulators()
1953 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, in tegra_pcie_get_legacy_regulators()
1954 sizeof(*pcie->supplies), in tegra_pcie_get_legacy_regulators()
1956 if (!pcie->supplies) in tegra_pcie_get_legacy_regulators()
1957 return -ENOMEM; in tegra_pcie_get_legacy_regulators()
1959 pcie->supplies[0].supply = "pex-clk"; in tegra_pcie_get_legacy_regulators()
1960 pcie->supplies[1].supply = "vdd"; in tegra_pcie_get_legacy_regulators()
1962 if (pcie->num_supplies > 2) in tegra_pcie_get_legacy_regulators()
1963 pcie->supplies[2].supply = "avdd"; in tegra_pcie_get_legacy_regulators()
1965 return devm_regulator_bulk_get(dev, pcie->num_supplies, pcie->supplies); in tegra_pcie_get_legacy_regulators()
1979 struct device *dev = pcie->dev; in tegra_pcie_get_regulators()
1980 struct device_node *np = dev->of_node; in tegra_pcie_get_regulators()
1983 if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) { in tegra_pcie_get_regulators()
1984 pcie->num_supplies = 4; in tegra_pcie_get_regulators()
1986 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, in tegra_pcie_get_regulators()
1987 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
1989 if (!pcie->supplies) in tegra_pcie_get_regulators()
1990 return -ENOMEM; in tegra_pcie_get_regulators()
1992 pcie->supplies[i++].supply = "dvdd-pex"; in tegra_pcie_get_regulators()
1993 pcie->supplies[i++].supply = "hvdd-pex-pll"; in tegra_pcie_get_regulators()
1994 pcie->supplies[i++].supply = "hvdd-pex"; in tegra_pcie_get_regulators()
1995 pcie->supplies[i++].supply = "vddio-pexctl-aud"; in tegra_pcie_get_regulators()
1996 } else if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) { in tegra_pcie_get_regulators()
1997 pcie->num_supplies = 3; in tegra_pcie_get_regulators()
1999 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, in tegra_pcie_get_regulators()
2000 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
2002 if (!pcie->supplies) in tegra_pcie_get_regulators()
2003 return -ENOMEM; in tegra_pcie_get_regulators()
2005 pcie->supplies[i++].supply = "hvddio-pex"; in tegra_pcie_get_regulators()
2006 pcie->supplies[i++].supply = "dvddio-pex"; in tegra_pcie_get_regulators()
2007 pcie->supplies[i++].supply = "vddio-pex-ctl"; in tegra_pcie_get_regulators()
2008 } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) { in tegra_pcie_get_regulators()
2009 pcie->num_supplies = 4; in tegra_pcie_get_regulators()
2011 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, in tegra_pcie_get_regulators()
2012 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
2014 if (!pcie->supplies) in tegra_pcie_get_regulators()
2015 return -ENOMEM; in tegra_pcie_get_regulators()
2017 pcie->supplies[i++].supply = "avddio-pex"; in tegra_pcie_get_regulators()
2018 pcie->supplies[i++].supply = "dvddio-pex"; in tegra_pcie_get_regulators()
2019 pcie->supplies[i++].supply = "hvdd-pex"; in tegra_pcie_get_regulators()
2020 pcie->supplies[i++].supply = "vddio-pex-ctl"; in tegra_pcie_get_regulators()
2021 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { in tegra_pcie_get_regulators()
2032 pcie->num_supplies = 4 + (need_pexa ? 2 : 0) + in tegra_pcie_get_regulators()
2035 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, in tegra_pcie_get_regulators()
2036 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
2038 if (!pcie->supplies) in tegra_pcie_get_regulators()
2039 return -ENOMEM; in tegra_pcie_get_regulators()
2041 pcie->supplies[i++].supply = "avdd-pex-pll"; in tegra_pcie_get_regulators()
2042 pcie->supplies[i++].supply = "hvdd-pex"; in tegra_pcie_get_regulators()
2043 pcie->supplies[i++].supply = "vddio-pex-ctl"; in tegra_pcie_get_regulators()
2044 pcie->supplies[i++].supply = "avdd-plle"; in tegra_pcie_get_regulators()
2047 pcie->supplies[i++].supply = "avdd-pexa"; in tegra_pcie_get_regulators()
2048 pcie->supplies[i++].supply = "vdd-pexa"; in tegra_pcie_get_regulators()
2052 pcie->supplies[i++].supply = "avdd-pexb"; in tegra_pcie_get_regulators()
2053 pcie->supplies[i++].supply = "vdd-pexb"; in tegra_pcie_get_regulators()
2055 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { in tegra_pcie_get_regulators()
2056 pcie->num_supplies = 5; in tegra_pcie_get_regulators()
2058 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, in tegra_pcie_get_regulators()
2059 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
2061 if (!pcie->supplies) in tegra_pcie_get_regulators()
2062 return -ENOMEM; in tegra_pcie_get_regulators()
2064 pcie->supplies[0].supply = "avdd-pex"; in tegra_pcie_get_regulators()
2065 pcie->supplies[1].supply = "vdd-pex"; in tegra_pcie_get_regulators()
2066 pcie->supplies[2].supply = "avdd-pex-pll"; in tegra_pcie_get_regulators()
2067 pcie->supplies[3].supply = "avdd-plle"; in tegra_pcie_get_regulators()
2068 pcie->supplies[4].supply = "vddio-pex-clk"; in tegra_pcie_get_regulators()
2071 if (of_regulator_bulk_available(dev->of_node, pcie->supplies, in tegra_pcie_get_regulators()
2072 pcie->num_supplies)) in tegra_pcie_get_regulators()
2073 return devm_regulator_bulk_get(dev, pcie->num_supplies, in tegra_pcie_get_regulators()
2074 pcie->supplies); in tegra_pcie_get_regulators()
2083 devm_kfree(dev, pcie->supplies); in tegra_pcie_get_regulators()
2084 pcie->num_supplies = 0; in tegra_pcie_get_regulators()
2091 struct device *dev = pcie->dev; in tegra_pcie_parse_dt()
2092 struct device_node *np = dev->of_node, *port; in tegra_pcie_parse_dt()
2093 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_parse_dt()
2113 if (index < 1 || index > soc->num_ports) { in tegra_pcie_parse_dt()
2115 err = -EINVAL; in tegra_pcie_parse_dt()
2119 index--; in tegra_pcie_parse_dt()
2121 err = of_property_read_u32(port, "nvidia,num-lanes", &value); in tegra_pcie_parse_dt()
2130 err = -EINVAL; in tegra_pcie_parse_dt()
2141 mask |= ((1 << value) - 1) << lane; in tegra_pcie_parse_dt()
2146 err = -ENOMEM; in tegra_pcie_parse_dt()
2150 err = of_address_to_resource(port, 0, &rp->regs); in tegra_pcie_parse_dt()
2156 INIT_LIST_HEAD(&rp->list); in tegra_pcie_parse_dt()
2157 rp->index = index; in tegra_pcie_parse_dt()
2158 rp->lanes = value; in tegra_pcie_parse_dt()
2159 rp->pcie = pcie; in tegra_pcie_parse_dt()
2160 rp->np = port; in tegra_pcie_parse_dt()
2162 rp->base = devm_pci_remap_cfg_resource(dev, &rp->regs); in tegra_pcie_parse_dt()
2163 if (IS_ERR(rp->base)) in tegra_pcie_parse_dt()
2164 return PTR_ERR(rp->base); in tegra_pcie_parse_dt()
2166 label = devm_kasprintf(dev, GFP_KERNEL, "pex-reset-%u", index); in tegra_pcie_parse_dt()
2169 return -ENOMEM; in tegra_pcie_parse_dt()
2173 * Returns -ENOENT if reset-gpios property is not populated in tegra_pcie_parse_dt()
2177 rp->reset_gpio = devm_gpiod_get_from_of_node(dev, port, in tegra_pcie_parse_dt()
2178 "reset-gpios", 0, in tegra_pcie_parse_dt()
2181 if (IS_ERR(rp->reset_gpio)) { in tegra_pcie_parse_dt()
2182 if (PTR_ERR(rp->reset_gpio) == -ENOENT) { in tegra_pcie_parse_dt()
2183 rp->reset_gpio = NULL; in tegra_pcie_parse_dt()
2186 PTR_ERR(rp->reset_gpio)); in tegra_pcie_parse_dt()
2187 return PTR_ERR(rp->reset_gpio); in tegra_pcie_parse_dt()
2191 list_add_tail(&rp->list, &pcie->ports); in tegra_pcie_parse_dt()
2194 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config); in tegra_pcie_parse_dt()
2219 struct device *dev = port->pcie->dev; in tegra_pcie_port_check_link()
2224 value = readl(port->base + RP_PRIV_MISC); in tegra_pcie_port_check_link()
2227 writel(value, port->base + RP_PRIV_MISC); in tegra_pcie_port_check_link()
2233 value = readl(port->base + RP_VEND_XP); in tegra_pcie_port_check_link()
2239 } while (--timeout); in tegra_pcie_port_check_link()
2242 dev_dbg(dev, "link %u down, retrying\n", port->index); in tegra_pcie_port_check_link()
2249 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_port_check_link()
2255 } while (--timeout); in tegra_pcie_port_check_link()
2259 } while (--retries); in tegra_pcie_port_check_link()
2266 struct device *dev = pcie->dev; in tegra_pcie_change_link_speed()
2271 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_change_link_speed()
2278 value = readl(port->base + RP_LINK_CONTROL_STATUS_2); in tegra_pcie_change_link_speed()
2281 writel(value, port->base + RP_LINK_CONTROL_STATUS_2); in tegra_pcie_change_link_speed()
2290 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_change_link_speed()
2299 port->index); in tegra_pcie_change_link_speed()
2302 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_change_link_speed()
2304 writel(value, port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_change_link_speed()
2309 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_change_link_speed()
2318 port->index); in tegra_pcie_change_link_speed()
2324 struct device *dev = pcie->dev; in tegra_pcie_enable_ports()
2327 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in tegra_pcie_enable_ports()
2329 port->index, port->lanes); in tegra_pcie_enable_ports()
2335 reset_control_deassert(pcie->pcie_xrst); in tegra_pcie_enable_ports()
2337 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in tegra_pcie_enable_ports()
2341 dev_info(dev, "link %u down, ignoring\n", port->index); in tegra_pcie_enable_ports()
2347 if (pcie->soc->has_gen2) in tegra_pcie_enable_ports()
2355 reset_control_assert(pcie->pcie_xrst); in tegra_pcie_disable_ports()
2357 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in tegra_pcie_disable_ports()
2502 { .compatible = "nvidia,tegra186-pcie", .data = &tegra186_pcie },
2503 { .compatible = "nvidia,tegra210-pcie", .data = &tegra210_pcie },
2504 { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie },
2505 { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie },
2506 { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie },
2512 struct tegra_pcie *pcie = s->private; in tegra_pcie_ports_seq_start()
2514 if (list_empty(&pcie->ports)) in tegra_pcie_ports_seq_start()
2519 return seq_list_start(&pcie->ports, *pos); in tegra_pcie_ports_seq_start()
2524 struct tegra_pcie *pcie = s->private; in tegra_pcie_ports_seq_next()
2526 return seq_list_next(v, &pcie->ports, pos); in tegra_pcie_ports_seq_next()
2541 value = readl(port->base + RP_VEND_XP); in tegra_pcie_ports_seq_show()
2546 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_ports_seq_show()
2551 seq_printf(s, "%2u ", port->index); in tegra_pcie_ports_seq_show()
2578 debugfs_remove_recursive(pcie->debugfs); in tegra_pcie_debugfs_exit()
2579 pcie->debugfs = NULL; in tegra_pcie_debugfs_exit()
2584 pcie->debugfs = debugfs_create_dir("pcie", NULL); in tegra_pcie_debugfs_init()
2586 debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs, pcie, in tegra_pcie_debugfs_init()
2592 struct device *dev = &pdev->dev; in tegra_pcie_probe()
2599 return -ENOMEM; in tegra_pcie_probe()
2602 host->sysdata = pcie; in tegra_pcie_probe()
2605 pcie->soc = of_device_get_match_data(dev); in tegra_pcie_probe()
2606 INIT_LIST_HEAD(&pcie->ports); in tegra_pcie_probe()
2607 pcie->dev = dev; in tegra_pcie_probe()
2625 pm_runtime_enable(pcie->dev); in tegra_pcie_probe()
2626 err = pm_runtime_get_sync(pcie->dev); in tegra_pcie_probe()
2632 host->ops = &tegra_pcie_ops; in tegra_pcie_probe()
2633 host->map_irq = tegra_pcie_map_irq; in tegra_pcie_probe()
2647 pm_runtime_put_sync(pcie->dev); in tegra_pcie_probe()
2648 pm_runtime_disable(pcie->dev); in tegra_pcie_probe()
2664 pci_stop_root_bus(host->bus); in tegra_pcie_remove()
2665 pci_remove_root_bus(host->bus); in tegra_pcie_remove()
2666 pm_runtime_put_sync(pcie->dev); in tegra_pcie_remove()
2667 pm_runtime_disable(pcie->dev); in tegra_pcie_remove()
2674 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in tegra_pcie_remove()
2686 list_for_each_entry(port, &pcie->ports, list) in tegra_pcie_pm_suspend()
2697 if (pcie->soc->program_uphy) { in tegra_pcie_pm_suspend()
2703 reset_control_assert(pcie->pex_rst); in tegra_pcie_pm_suspend()
2704 clk_disable_unprepare(pcie->pex_clk); in tegra_pcie_pm_suspend()
2738 err = clk_prepare_enable(pcie->pex_clk); in tegra_pcie_pm_resume()
2744 reset_control_deassert(pcie->pex_rst); in tegra_pcie_pm_resume()
2746 if (pcie->soc->program_uphy) { in tegra_pcie_pm_resume()
2760 reset_control_assert(pcie->pex_rst); in tegra_pcie_pm_resume()
2761 clk_disable_unprepare(pcie->pex_clk); in tegra_pcie_pm_resume()
2778 .name = "tegra-pcie",