45 #define APPL_CTRL				0x4  macro
462 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_hot_rst_done()
464 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_hot_rst_done()
914 	val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_prepare_host()
916 	appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_prepare_host()
958 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_host_init()
960 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_host_init()
1350 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_config_controller()
1354 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_config_controller()
1372 	val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_config_controller()
1373 	appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);  in tegra_pcie_config_controller()
1530 			data = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_pme_turnoff()
1532 			appl_writel(pcie, data, APPL_CTRL);  in tegra_pcie_dw_pme_turnoff()
1622 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_assert()
1624 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_assert()
1719 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1722 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1793 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1795 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
2207 	val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_suspend_late()
2211 	appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_suspend_late()
2269 	val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_resume_early()
2275 	appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_resume_early()