327 		dev_err(dev, "cannot enable regulators\n");  in qcom_pcie_init_2_1_0()
333 		dev_err(dev, "cannot deassert ahb reset\n");  in qcom_pcie_init_2_1_0()
339 		dev_err(dev, "cannot deassert ext reset\n");  in qcom_pcie_init_2_1_0()
345 		dev_err(dev, "cannot deassert phy reset\n");  in qcom_pcie_init_2_1_0()
351 		dev_err(dev, "cannot deassert pci reset\n");  in qcom_pcie_init_2_1_0()
357 		dev_err(dev, "cannot deassert por reset\n");  in qcom_pcie_init_2_1_0()
363 		dev_err(dev, "cannot deassert axi reset\n");  in qcom_pcie_init_2_1_0()
482 		dev_err(dev, "cannot deassert core reset\n");  in qcom_pcie_init_1_0_0()
488 		dev_err(dev, "cannot prepare/enable aux clock\n");  in qcom_pcie_init_1_0_0()
494 		dev_err(dev, "cannot prepare/enable iface clock\n");  in qcom_pcie_init_1_0_0()
500 		dev_err(dev, "cannot prepare/enable master_bus clock\n");  in qcom_pcie_init_1_0_0()
506 		dev_err(dev, "cannot prepare/enable slave_bus clock\n");  in qcom_pcie_init_1_0_0()
512 		dev_err(dev, "cannot enable vdda regulator\n");  in qcom_pcie_init_1_0_0()
614 		dev_err(dev, "cannot enable regulators\n");  in qcom_pcie_init_2_3_2()
620 		dev_err(dev, "cannot prepare/enable aux clock\n");  in qcom_pcie_init_2_3_2()
626 		dev_err(dev, "cannot prepare/enable cfg clock\n");  in qcom_pcie_init_2_3_2()
632 		dev_err(dev, "cannot prepare/enable master clock\n");  in qcom_pcie_init_2_3_2()
638 		dev_err(dev, "cannot prepare/enable slave clock\n");  in qcom_pcie_init_2_3_2()
687 		dev_err(dev, "cannot prepare/enable pipe clock\n");  in qcom_pcie_post_init_2_3_2()
803 		dev_err(dev, "cannot assert axi master reset\n");  in qcom_pcie_init_2_4_0()
809 		dev_err(dev, "cannot assert axi slave reset\n");  in qcom_pcie_init_2_4_0()
817 		dev_err(dev, "cannot assert pipe reset\n");  in qcom_pcie_init_2_4_0()
823 		dev_err(dev, "cannot assert pipe sticky reset\n");  in qcom_pcie_init_2_4_0()
829 		dev_err(dev, "cannot assert phy reset\n");  in qcom_pcie_init_2_4_0()
835 		dev_err(dev, "cannot assert phy ahb reset\n");  in qcom_pcie_init_2_4_0()
843 		dev_err(dev, "cannot assert axi master sticky reset\n");  in qcom_pcie_init_2_4_0()
849 		dev_err(dev, "cannot assert power reset\n");  in qcom_pcie_init_2_4_0()
855 		dev_err(dev, "cannot assert ahb reset\n");  in qcom_pcie_init_2_4_0()
863 		dev_err(dev, "cannot deassert phy ahb reset\n");  in qcom_pcie_init_2_4_0()
869 		dev_err(dev, "cannot deassert phy reset\n");  in qcom_pcie_init_2_4_0()
875 		dev_err(dev, "cannot deassert pipe reset\n");  in qcom_pcie_init_2_4_0()
881 		dev_err(dev, "cannot deassert pipe sticky reset\n");  in qcom_pcie_init_2_4_0()
889 		dev_err(dev, "cannot deassert axi master reset\n");  in qcom_pcie_init_2_4_0()
895 		dev_err(dev, "cannot deassert axi master sticky reset\n");  in qcom_pcie_init_2_4_0()
901 		dev_err(dev, "cannot deassert axi slave reset\n");  in qcom_pcie_init_2_4_0()
907 		dev_err(dev, "cannot deassert power reset\n");  in qcom_pcie_init_2_4_0()
913 		dev_err(dev, "cannot deassert ahb reset\n");  in qcom_pcie_init_2_4_0()
1053 		dev_err(dev, "cannot prepare/enable core clock\n");  in qcom_pcie_init_2_3_3()
1059 		dev_err(dev, "cannot prepare/enable core clock\n");  in qcom_pcie_init_2_3_3()
1065 		dev_err(dev, "cannot prepare/enable axi slave clock\n");  in qcom_pcie_init_2_3_3()
1071 		dev_err(dev, "cannot prepare/enable ahb clock\n");  in qcom_pcie_init_2_3_3()
1077 		dev_err(dev, "cannot prepare/enable aux clock\n");  in qcom_pcie_init_2_3_3()
1171 		dev_err(dev, "cannot enable regulators\n");  in qcom_pcie_init_2_7_0()
1181 		dev_err(dev, "cannot deassert pci reset\n");  in qcom_pcie_init_2_7_0()
1189 		dev_err(dev, "cannot deassert pci reset\n");  in qcom_pcie_init_2_7_0()
1195 		dev_err(dev, "cannot prepare/enable pipe clock\n");  in qcom_pcie_init_2_7_0()
1453 		dev_err(dev, "cannot initialize host\n");  in qcom_pcie_probe()