Lines Matching full:mmio
203 void __iomem *mmio) in ndev_db_read() argument
208 return ndev->reg->db_ioread(mmio); in ndev_db_read()
212 void __iomem *mmio) in ndev_db_write() argument
220 ndev->reg->db_iowrite(db_bits, mmio); in ndev_db_write()
226 void __iomem *mmio) in ndev_db_set_mask() argument
239 ndev->reg->db_iowrite(ndev->db_mask, mmio); in ndev_db_set_mask()
247 void __iomem *mmio) in ndev_db_clear_mask() argument
260 ndev->reg->db_iowrite(ndev->db_mask, mmio); in ndev_db_clear_mask()
297 void __iomem *mmio) in ndev_spad_read() argument
305 return ioread32(mmio + (idx << 2)); in ndev_spad_read()
309 void __iomem *mmio) in ndev_spad_write() argument
317 iowrite32(val, mmio + (idx << 2)); in ndev_spad_write()
496 void __iomem *mmio; in ndev_ntb_debugfs_read() local
504 mmio = ndev->self_mmio; in ndev_ntb_debugfs_read()
569 u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask); in ndev_ntb_debugfs_read()
573 u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_bell); in ndev_ntb_debugfs_read()
615 u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 2)); in ndev_ntb_debugfs_read()
620 u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 4)); in ndev_ntb_debugfs_read()
624 u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 5)); in ndev_ntb_debugfs_read()
628 u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_xlat, 4)); in ndev_ntb_debugfs_read()
633 u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 2)); in ndev_ntb_debugfs_read()
638 u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 4)); in ndev_ntb_debugfs_read()
641 u.v32 = ioread32(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 5)); in ndev_ntb_debugfs_read()
645 u.v64 = ioread64(mmio + bar2_off(ndev->xlat_reg->bar2_limit, 4)); in ndev_ntb_debugfs_read()
655 u.v64 = ioread64(mmio + XEON_PBAR23XLAT_OFFSET); in ndev_ntb_debugfs_read()
660 u.v32 = ioread32(mmio + XEON_PBAR4XLAT_OFFSET); in ndev_ntb_debugfs_read()
664 u.v32 = ioread32(mmio + XEON_PBAR5XLAT_OFFSET); in ndev_ntb_debugfs_read()
669 u.v64 = ioread64(mmio + XEON_PBAR45XLAT_OFFSET); in ndev_ntb_debugfs_read()
675 u.v64 = ioread64(mmio + XEON_PBAR23LMT_OFFSET); in ndev_ntb_debugfs_read()
680 u.v32 = ioread32(mmio + XEON_PBAR4LMT_OFFSET); in ndev_ntb_debugfs_read()
684 u.v32 = ioread32(mmio + XEON_PBAR5LMT_OFFSET); in ndev_ntb_debugfs_read()
689 u.v64 = ioread64(mmio + XEON_PBAR45LMT_OFFSET); in ndev_ntb_debugfs_read()
698 u.v64 = ioread64(mmio + XEON_SBAR0BASE_OFFSET); in ndev_ntb_debugfs_read()
702 u.v64 = ioread64(mmio + XEON_SBAR23BASE_OFFSET); in ndev_ntb_debugfs_read()
707 u.v32 = ioread32(mmio + XEON_SBAR4BASE_OFFSET); in ndev_ntb_debugfs_read()
710 u.v32 = ioread32(mmio + XEON_SBAR5BASE_OFFSET); in ndev_ntb_debugfs_read()
714 u.v64 = ioread64(mmio + XEON_SBAR45BASE_OFFSET); in ndev_ntb_debugfs_read()
724 u.v16 = ioread16(mmio + XEON_USMEMMISS_OFFSET); in ndev_ntb_debugfs_read()
848 void __iomem *mmio; in intel_ntb_mw_set_trans() local
877 mmio = ndev->self_mmio; in intel_ntb_mw_set_trans()
883 base = ioread64(mmio + base_reg) & NTB_BAR_MASK_64; in intel_ntb_mw_set_trans()
892 iowrite64(addr, mmio + xlat_reg); in intel_ntb_mw_set_trans()
893 reg_val = ioread64(mmio + xlat_reg); in intel_ntb_mw_set_trans()
895 iowrite64(0, mmio + xlat_reg); in intel_ntb_mw_set_trans()
900 iowrite64(limit, mmio + limit_reg); in intel_ntb_mw_set_trans()
901 reg_val = ioread64(mmio + limit_reg); in intel_ntb_mw_set_trans()
903 iowrite64(base, mmio + limit_reg); in intel_ntb_mw_set_trans()
904 iowrite64(0, mmio + xlat_reg); in intel_ntb_mw_set_trans()
914 base = ioread32(mmio + base_reg) & NTB_BAR_MASK_32; in intel_ntb_mw_set_trans()
923 iowrite32(addr, mmio + xlat_reg); in intel_ntb_mw_set_trans()
924 reg_val = ioread32(mmio + xlat_reg); in intel_ntb_mw_set_trans()
926 iowrite32(0, mmio + xlat_reg); in intel_ntb_mw_set_trans()
931 iowrite32(limit, mmio + limit_reg); in intel_ntb_mw_set_trans()
932 reg_val = ioread32(mmio + limit_reg); in intel_ntb_mw_set_trans()
934 iowrite32(base, mmio + limit_reg); in intel_ntb_mw_set_trans()
935 iowrite32(0, mmio + xlat_reg); in intel_ntb_mw_set_trans()
1208 static u64 xeon_db_ioread(const void __iomem *mmio) in xeon_db_ioread() argument
1210 return (u64)ioread16(mmio); in xeon_db_ioread()
1213 static void xeon_db_iowrite(u64 bits, void __iomem *mmio) in xeon_db_iowrite() argument
1215 iowrite16((u16)bits, mmio); in xeon_db_iowrite()
1296 void __iomem *mmio; in xeon_setup_b2b_mw() local
1303 mmio = ndev->self_mmio; in xeon_setup_b2b_mw()
1404 iowrite64(bar_addr, mmio + XEON_SBAR0BASE_OFFSET); in xeon_setup_b2b_mw()
1412 iowrite64(bar_addr, mmio + XEON_SBAR23BASE_OFFSET); in xeon_setup_b2b_mw()
1413 bar_addr = ioread64(mmio + XEON_SBAR23BASE_OFFSET); in xeon_setup_b2b_mw()
1419 iowrite64(bar_addr, mmio + XEON_SBAR45BASE_OFFSET); in xeon_setup_b2b_mw()
1420 bar_addr = ioread64(mmio + XEON_SBAR45BASE_OFFSET); in xeon_setup_b2b_mw()
1425 iowrite32(bar_addr, mmio + XEON_SBAR4BASE_OFFSET); in xeon_setup_b2b_mw()
1426 bar_addr = ioread32(mmio + XEON_SBAR4BASE_OFFSET); in xeon_setup_b2b_mw()
1431 iowrite32(bar_addr, mmio + XEON_SBAR5BASE_OFFSET); in xeon_setup_b2b_mw()
1432 bar_addr = ioread32(mmio + XEON_SBAR5BASE_OFFSET); in xeon_setup_b2b_mw()
1439 iowrite64(bar_addr, mmio + XEON_SBAR23LMT_OFFSET); in xeon_setup_b2b_mw()
1440 bar_addr = ioread64(mmio + XEON_SBAR23LMT_OFFSET); in xeon_setup_b2b_mw()
1446 iowrite64(bar_addr, mmio + XEON_SBAR45LMT_OFFSET); in xeon_setup_b2b_mw()
1447 bar_addr = ioread64(mmio + XEON_SBAR45LMT_OFFSET); in xeon_setup_b2b_mw()
1452 iowrite32(bar_addr, mmio + XEON_SBAR4LMT_OFFSET); in xeon_setup_b2b_mw()
1453 bar_addr = ioread32(mmio + XEON_SBAR4LMT_OFFSET); in xeon_setup_b2b_mw()
1458 iowrite32(bar_addr, mmio + XEON_SBAR5LMT_OFFSET); in xeon_setup_b2b_mw()
1459 bar_addr = ioread32(mmio + XEON_SBAR5LMT_OFFSET); in xeon_setup_b2b_mw()
1464 iowrite64(0, mmio + XEON_SBAR23XLAT_OFFSET); in xeon_setup_b2b_mw()
1467 iowrite64(0, mmio + XEON_SBAR45XLAT_OFFSET); in xeon_setup_b2b_mw()
1469 iowrite32(0, mmio + XEON_SBAR4XLAT_OFFSET); in xeon_setup_b2b_mw()
1470 iowrite32(0, mmio + XEON_SBAR5XLAT_OFFSET); in xeon_setup_b2b_mw()
1474 iowrite64(0, mmio + XEON_PBAR23LMT_OFFSET); in xeon_setup_b2b_mw()
1476 iowrite64(0, mmio + XEON_PBAR45LMT_OFFSET); in xeon_setup_b2b_mw()
1478 iowrite32(0, mmio + XEON_PBAR4LMT_OFFSET); in xeon_setup_b2b_mw()
1479 iowrite32(0, mmio + XEON_PBAR5LMT_OFFSET); in xeon_setup_b2b_mw()
1484 iowrite64(bar_addr, mmio + XEON_PBAR23XLAT_OFFSET); in xeon_setup_b2b_mw()
1485 bar_addr = ioread64(mmio + XEON_PBAR23XLAT_OFFSET); in xeon_setup_b2b_mw()
1490 iowrite64(bar_addr, mmio + XEON_PBAR45XLAT_OFFSET); in xeon_setup_b2b_mw()
1491 bar_addr = ioread64(mmio + XEON_PBAR45XLAT_OFFSET); in xeon_setup_b2b_mw()
1495 iowrite32(bar_addr, mmio + XEON_PBAR4XLAT_OFFSET); in xeon_setup_b2b_mw()
1496 bar_addr = ioread32(mmio + XEON_PBAR4XLAT_OFFSET); in xeon_setup_b2b_mw()
1500 iowrite32(bar_addr, mmio + XEON_PBAR5XLAT_OFFSET); in xeon_setup_b2b_mw()
1501 bar_addr = ioread32(mmio + XEON_PBAR5XLAT_OFFSET); in xeon_setup_b2b_mw()
1521 iowrite32(bar_addr, mmio + XEON_B2B_XLAT_OFFSETL); in xeon_setup_b2b_mw()
1522 iowrite32(bar_addr >> 32, mmio + XEON_B2B_XLAT_OFFSETU); in xeon_setup_b2b_mw()
1525 /* map peer ntb mmio config space registers */ in xeon_setup_b2b_mw()
1653 * B2BDOORBELL in conjunction with inbound access to NTB MMIO Space, in xeon_init_dev()