Lines Matching +full:12 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
21 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8821ce_efuse_parsing()
26 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_read_efuse()
32 efuse->rfe_option = map->rfe_option; in rtw8821c_read_efuse()
33 efuse->rf_board_option = map->rf_board_option; in rtw8821c_read_efuse()
34 efuse->crystal_cap = map->xtal_k; in rtw8821c_read_efuse()
35 efuse->pa_type_2g = map->pa_type; in rtw8821c_read_efuse()
36 efuse->pa_type_5g = map->pa_type; in rtw8821c_read_efuse()
37 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8821c_read_efuse()
38 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8821c_read_efuse()
39 efuse->channel_plan = map->channel_plan; in rtw8821c_read_efuse()
40 efuse->country_code[0] = map->country_code[0]; in rtw8821c_read_efuse()
41 efuse->country_code[1] = map->country_code[1]; in rtw8821c_read_efuse()
42 efuse->bt_setting = map->rf_bt_setting; in rtw8821c_read_efuse()
43 efuse->regd = map->rf_board_option & 0x7; in rtw8821c_read_efuse()
44 efuse->thermal_meter[0] = map->thermal_meter; in rtw8821c_read_efuse()
45 efuse->thermal_meter_k = map->thermal_meter; in rtw8821c_read_efuse()
46 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g; in rtw8821c_read_efuse()
47 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g; in rtw8821c_read_efuse()
50 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; in rtw8821c_read_efuse()
58 return -ENOTSUPP; in rtw8821c_read_efuse()
88 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_pwrtrack_init()
92 dm_info->default_ofdm_index = 24; in rtw8821c_pwrtrack_init()
94 dm_info->default_ofdm_index = swing_idx; in rtw8821c_pwrtrack_init()
96 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]); in rtw8821c_pwrtrack_init()
97 dm_info->delta_power_index[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
98 dm_info->delta_power_index_last[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
99 dm_info->pwr_trk_triggered = false; in rtw8821c_pwrtrack_init()
100 dm_info->pwr_trk_init_trigger = true; in rtw8821c_pwrtrack_init()
101 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; in rtw8821c_pwrtrack_init()
140 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8821c_phy_set_param()
143 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); in rtw8821c_phy_set_param()
147 rtwdev->chip->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); in rtw8821c_phy_set_param()
148 rtwdev->chip->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD); in rtw8821c_phy_set_param()
149 rtwdev->chip->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD); in rtw8821c_phy_set_param()
152 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; in rtw8821c_phy_set_param()
180 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); in rtw8821c_mac_init()
193 /* Set beacon cotnrol - enable TSF and other related functions */ in rtw8821c_mac_init()
210 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); in rtw8821c_mac_init()
211 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, BIT(6)); in rtw8821c_mac_init()
223 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); in rtw8821c_cfg_ldo25()
260 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); in rtw8821c_set_channel_rf()
263 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); in rtw8821c_set_channel_rf()
268 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8821c_set_channel_rf()
269 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); in rtw8821c_set_channel_rf()
276 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
277 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
278 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
279 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
282 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
283 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); in rtw8821c_set_channel_rxdfir()
284 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
285 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
288 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
289 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
290 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
291 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
301 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8821c_set_channel_bb()
302 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); in rtw8821c_set_channel_bb()
303 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); in rtw8821c_set_channel_bb()
314 rtwdev->chip->ch_param[0]); in rtw8821c_set_channel_bb()
316 rtwdev->chip->ch_param[1] & MASKLWORD); in rtw8821c_set_channel_bb()
318 rtwdev->chip->ch_param[2]); in rtw8821c_set_channel_bb()
321 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); in rtw8821c_set_channel_bb()
322 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); in rtw8821c_set_channel_bb()
323 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8821c_set_channel_bb()
351 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
355 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); in rtw8821c_set_channel_bb()
357 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); in rtw8821c_set_channel_bb()
365 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
374 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
382 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
383 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
391 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
392 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
399 struct rtw_efuse efuse = rtwdev->efuse; in rtw8821c_get_bb_swing()
432 s8 min_rx_power = -120; in query_phy_status_page0()
435 pkt_stat->rx_power[RF_PATH_A] = pwdb - 100; in query_phy_status_page0()
436 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); in query_phy_status_page0()
437 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; in query_phy_status_page0()
438 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], in query_phy_status_page0()
446 s8 min_rx_power = -120; in query_phy_status_page1()
448 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) in query_phy_status_page1()
455 else if (rxsc >= 9 && rxsc <= 12) in query_phy_status_page1()
462 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; in query_phy_status_page1()
463 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); in query_phy_status_page1()
464 pkt_stat->bw = bw; in query_phy_status_page1()
465 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], in query_phy_status_page1()
494 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; in rtw8821c_query_rx_desc()
499 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); in rtw8821c_query_rx_desc()
500 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); in rtw8821c_query_rx_desc()
501 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); in rtw8821c_query_rx_desc()
502 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc); in rtw8821c_query_rx_desc()
503 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); in rtw8821c_query_rx_desc()
504 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); in rtw8821c_query_rx_desc()
505 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); in rtw8821c_query_rx_desc()
506 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); in rtw8821c_query_rx_desc()
507 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); in rtw8821c_query_rx_desc()
508 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); in rtw8821c_query_rx_desc()
509 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); in rtw8821c_query_rx_desc()
510 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); in rtw8821c_query_rx_desc()
512 /* drv_info_sz is in unit of 8-bytes */ in rtw8821c_query_rx_desc()
513 pkt_stat->drv_info_sz *= 8; in rtw8821c_query_rx_desc()
516 if (pkt_stat->is_c2h) in rtw8821c_query_rx_desc()
519 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + in rtw8821c_query_rx_desc()
520 pkt_stat->drv_info_sz); in rtw8821c_query_rx_desc()
521 if (pkt_stat->phy_status) { in rtw8821c_query_rx_desc()
522 phy_status = rx_desc + desc_sz + pkt_stat->shift; in rtw8821c_query_rx_desc()
532 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_tx_power_index_by_rate()
540 pwr_index = hal->tx_pwr_tbl[path][rate]; in rtw8821c_set_tx_power_index_by_rate()
554 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_tx_power_index()
557 for (path = 0; path < hal->rf_path_num; path++) { in rtw8821c_set_tx_power_index()
569 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_false_alarm_statistics()
576 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); in rtw8821c_false_alarm_statistics()
580 dm_info->cck_fa_cnt = cck_fa_cnt; in rtw8821c_false_alarm_statistics()
581 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; in rtw8821c_false_alarm_statistics()
583 dm_info->total_fa_cnt += cck_fa_cnt; in rtw8821c_false_alarm_statistics()
584 dm_info->total_fa_cnt = ofdm_fa_cnt; in rtw8821c_false_alarm_statistics()
587 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
588 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
591 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
592 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
595 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
596 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
599 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
600 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
603 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt); in rtw8821c_false_alarm_statistics()
604 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; in rtw8821c_false_alarm_statistics()
607 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); in rtw8821c_false_alarm_statistics()
608 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; in rtw8821c_false_alarm_statistics()
611 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); in rtw8821c_false_alarm_statistics()
612 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); in rtw8821c_false_alarm_statistics()
613 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15)); in rtw8821c_false_alarm_statistics()
614 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15)); in rtw8821c_false_alarm_statistics()
615 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
616 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
640 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); in rtw8821c_do_iqk()
665 /* enable PTA (3-wire function form BT side) */ in rtw8821c_coex_cfg_init()
676 /* beacon queue always hi-pri */ in rtw8821c_coex_cfg_init()
684 struct rtw_coex *coex = &rtwdev->coex; in rtw8821c_coex_cfg_ant_switch()
685 struct rtw_coex_dm *coex_dm = &coex->dm; in rtw8821c_coex_cfg_ant_switch()
686 struct rtw_coex_rfe *coex_rfe = &coex->rfe; in rtw8821c_coex_cfg_ant_switch()
691 if (switch_status == coex_dm->cur_switch_status) in rtw8821c_coex_cfg_ant_switch()
694 coex_dm->cur_switch_status = switch_status; in rtw8821c_coex_cfg_ant_switch()
696 if (coex_rfe->ant_switch_diversity && in rtw8821c_coex_cfg_ant_switch()
700 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); in rtw8821c_coex_cfg_ant_switch()
712 if (coex_rfe->rfe_module_type != 0x4 && in rtw8821c_coex_cfg_ant_switch()
713 coex_rfe->rfe_module_type != 0x2) in rtw8821c_coex_cfg_ant_switch()
784 struct rtw_coex *coex = &rtwdev->coex; in rtw8821c_coex_cfg_rfe_type()
785 struct rtw_coex_rfe *coex_rfe = &coex->rfe; in rtw8821c_coex_cfg_rfe_type()
786 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_coex_cfg_rfe_type()
788 coex_rfe->rfe_module_type = efuse->rfe_option; in rtw8821c_coex_cfg_rfe_type()
789 coex_rfe->ant_switch_polarity = 0; in rtw8821c_coex_cfg_rfe_type()
790 coex_rfe->ant_switch_exist = true; in rtw8821c_coex_cfg_rfe_type()
791 coex_rfe->wlg_at_btg = false; in rtw8821c_coex_cfg_rfe_type()
793 switch (coex_rfe->rfe_module_type) { in rtw8821c_coex_cfg_rfe_type()
797 case 9: /* 1-Ant, Main, WLG */ in rtw8821c_coex_cfg_rfe_type()
798 default: /* 2-Ant, DPDT, WLG */ in rtw8821c_coex_cfg_rfe_type()
801 case 10: /* 1-Ant, Main, BTG */ in rtw8821c_coex_cfg_rfe_type()
803 case 15: /* 2-Ant, DPDT, BTG */ in rtw8821c_coex_cfg_rfe_type()
804 coex_rfe->wlg_at_btg = true; in rtw8821c_coex_cfg_rfe_type()
807 case 11: /* 1-Ant, Aux, WLG */ in rtw8821c_coex_cfg_rfe_type()
808 coex_rfe->ant_switch_polarity = 1; in rtw8821c_coex_cfg_rfe_type()
811 case 12: /* 1-Ant, Aux, BTG */ in rtw8821c_coex_cfg_rfe_type()
812 coex_rfe->wlg_at_btg = true; in rtw8821c_coex_cfg_rfe_type()
813 coex_rfe->ant_switch_polarity = 1; in rtw8821c_coex_cfg_rfe_type()
816 case 13: /* 2-Ant, no switch, WLG */ in rtw8821c_coex_cfg_rfe_type()
818 case 14: /* 2-Ant, no antenna switch, WLG */ in rtw8821c_coex_cfg_rfe_type()
819 coex_rfe->ant_switch_exist = false; in rtw8821c_coex_cfg_rfe_type()
826 struct rtw_coex *coex = &rtwdev->coex; in rtw8821c_coex_cfg_wl_tx_power()
827 struct rtw_coex_dm *coex_dm = &coex->dm; in rtw8821c_coex_cfg_wl_tx_power()
828 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_coex_cfg_wl_tx_power()
829 bool share_ant = efuse->share_ant; in rtw8821c_coex_cfg_wl_tx_power()
834 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) in rtw8821c_coex_cfg_wl_tx_power()
837 coex_dm->cur_wl_pwr_lvl = wl_pwr; in rtw8821c_coex_cfg_wl_tx_power()
848 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_txagc_swing_offset()
849 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A]; in rtw8821c_txagc_swing_offset()
850 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; in rtw8821c_txagc_swing_offset()
854 u8 swing_index = dm_info->default_ofdm_index; in rtw8821c_txagc_swing_offset()
857 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15); in rtw8821c_txagc_swing_offset()
862 swing_index = dm_info->default_ofdm_index; in rtw8821c_txagc_swing_offset()
865 swing_index = dm_info->default_ofdm_index + in rtw8821c_txagc_swing_offset()
866 delta_pwr_idx - pwr_idx_offset; in rtw8821c_txagc_swing_offset()
872 swing_index = dm_info->default_ofdm_index; in rtw8821c_txagc_swing_offset()
874 if (dm_info->default_ofdm_index > in rtw8821c_txagc_swing_offset()
875 (pwr_idx_offset_lower - delta_pwr_idx)) in rtw8821c_txagc_swing_offset()
876 swing_index = dm_info->default_ofdm_index + in rtw8821c_txagc_swing_offset()
877 delta_pwr_idx - pwr_idx_offset_lower; in rtw8821c_txagc_swing_offset()
887 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1; in rtw8821c_txagc_swing_offset()
909 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_pwrtrack_set()
912 u8 channel = rtwdev->hal.current_channel; in rtw8821c_pwrtrack_set()
913 u8 band_width = rtwdev->hal.current_band_width; in rtw8821c_pwrtrack_set()
914 u8 regd = rtwdev->regd.txpwr_regd; in rtw8821c_pwrtrack_set()
915 u8 tx_rate = dm_info->tx_rate; in rtw8821c_pwrtrack_set()
916 u8 max_pwr_idx = rtwdev->chip->max_power_index; in rtw8821c_pwrtrack_set()
923 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; in rtw8821c_pwrtrack_set()
924 pwr_idx_offset_lower = 0 - tx_pwr_idx; in rtw8821c_pwrtrack_set()
931 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_phy_pwrtrack()
937 if (rtwdev->efuse.thermal_meter[0] == 0xff) in rtw8821c_phy_pwrtrack()
944 if (dm_info->pwr_trk_init_trigger) in rtw8821c_phy_pwrtrack()
945 dm_info->pwr_trk_init_trigger = false; in rtw8821c_phy_pwrtrack()
952 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); in rtw8821c_phy_pwrtrack()
954 dm_info->delta_power_index[RF_PATH_A] = in rtw8821c_phy_pwrtrack()
957 if (dm_info->delta_power_index[RF_PATH_A] == in rtw8821c_phy_pwrtrack()
958 dm_info->delta_power_index_last[RF_PATH_A]) in rtw8821c_phy_pwrtrack()
961 dm_info->delta_power_index_last[RF_PATH_A] = in rtw8821c_phy_pwrtrack()
962 dm_info->delta_power_index[RF_PATH_A]; in rtw8821c_phy_pwrtrack()
972 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_pwr_track()
973 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_pwr_track()
975 if (efuse->power_track_type != 0) in rtw8821c_pwr_track()
978 if (!dm_info->pwr_trk_triggered) { in rtw8821c_pwr_track()
981 dm_info->pwr_trk_triggered = true; in rtw8821c_pwr_track()
986 dm_info->pwr_trk_triggered = false; in rtw8821c_pwr_track()
1012 if (bfee->role == RTW_BFEE_SU) in rtw8821c_bf_config_bfee()
1014 else if (bfee->role == RTW_BFEE_MU) in rtw8821c_bf_config_bfee()
1022 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_phy_cck_pd_set()
1025 if (dm_info->min_rssi > 60) { in rtw8821c_phy_cck_pd_set()
1031 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) in rtw8821c_phy_cck_pd_set()
1034 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; in rtw8821c_phy_cck_pd_set()
1037 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; in rtw8821c_phy_cck_pd_set()
1040 dm_info->cck_pd_default + new_lvl * 2); in rtw8821c_phy_cck_pd_set()
1048 RTW_PWR_CMD_WRITE, BIT(0), 0},
1053 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1058 RTW_PWR_CMD_WRITE, BIT(0), 0},
1063 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1086 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1096 RTW_PWR_CMD_WRITE, BIT(5), 0},
1101 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1106 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1111 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1116 RTW_PWR_CMD_WRITE, BIT(0), 0},
1121 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1126 RTW_PWR_CMD_WRITE, BIT(7), 0},
1131 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1136 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1141 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1146 RTW_PWR_CMD_POLLING, BIT(0), 0},
1151 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1156 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1161 RTW_PWR_CMD_WRITE, BIT(1), 0},
1166 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
1167 (BIT(7) | BIT(6) | BIT(5))},
1172 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1177 RTW_PWR_CMD_WRITE, BIT(1), 0},
1190 RTW_PWR_CMD_WRITE, BIT(3), 0},
1200 RTW_PWR_CMD_WRITE, BIT(1), 0},
1205 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1210 RTW_PWR_CMD_WRITE, BIT(1), 0},
1215 RTW_PWR_CMD_WRITE, BIT(0), 0},
1220 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1225 RTW_PWR_CMD_POLLING, BIT(1), 0},
1230 RTW_PWR_CMD_WRITE, BIT(3), 0},
1235 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1253 RTW_PWR_CMD_WRITE, BIT(5), 0},
1258 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1263 RTW_PWR_CMD_WRITE, BIT(0), 0},
1268 RTW_PWR_CMD_WRITE, BIT(5), 0},
1273 RTW_PWR_CMD_WRITE, BIT(4), 0},
1278 RTW_PWR_CMD_WRITE, BIT(0), 0},
1283 RTW_PWR_CMD_WRITE, BIT(1), 0},
1288 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1293 RTW_PWR_CMD_WRITE, BIT(2), 0},
1298 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1303 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1308 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1313 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1318 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1323 RTW_PWR_CMD_POLLING, BIT(1), 0},
1328 RTW_PWR_CMD_WRITE, BIT(1), 0},
1497 /* rssi in percentage % (dbm = % - 100) */
1501 /* Shared-Antenna Coex Table */
1503 {0x55555555, 0x55555555}, /* case-0 */
1508 {0xfafafafa, 0xfafafafa}, /* case-5 */
1513 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1518 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1523 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1528 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1533 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1538 /* Non-Shared-Antenna Coex Table */
1540 {0xffffffff, 0xffffffff}, /* case-100 */
1545 {0xffffffff, 0xffffffff}, /* case-105 */
1550 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1555 {0xffff55ff, 0xffff55ff}, /* case-115 */
1560 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1566 /* Shared-Antenna TDMA */
1568 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1569 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1573 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1578 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1583 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1588 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1593 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1598 /* Non-Shared-Antenna TDMA */
1600 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1605 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1610 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1615 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1620 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1629 {0, 20, false, 7}, /* for WL-CPT */
1638 {0, 20, false, 7}, /* for WL-CPT */
1649 11, 11, 12, 12, 12, 12, 12},
1651 11, 12, 12, 12, 12, 12, 12, 12},
1653 11, 12, 12, 12, 12, 12, 12},
1658 12, 12, 12, 12, 12, 12, 12},
1660 12, 12, 12, 12, 12, 12, 12, 12},
1662 11, 12, 12, 12, 12, 12, 12, 12},
1667 11, 11, 12, 12, 12, 12, 12},
1669 11, 12, 12, 12, 12, 12, 12, 12},
1671 11, 12, 12, 12, 12, 12, 12},
1676 12, 12, 12, 12, 12, 12, 12},
1678 12, 12, 12, 12, 12, 12, 12, 12},
1680 11, 12, 12, 12, 12, 12, 12, 12},
1755 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1758 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1759 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1760 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1761 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1766 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1794 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),