Lines Matching +full:0 +full:x20020000
37 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8821c_read_efuse()
38 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8821c_read_efuse()
40 efuse->country_code[0] = map->country_code[0]; in rtw8821c_read_efuse()
43 efuse->regd = map->rf_board_option & 0x7; in rtw8821c_read_efuse()
44 efuse->thermal_meter[0] = map->thermal_meter; in rtw8821c_read_efuse()
49 for (i = 0; i < 4; i++) in rtw8821c_read_efuse()
61 return 0; in rtw8821c_read_efuse()
65 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
66 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
67 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
68 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
73 u8 i = 0; in rtw8821c_get_swing_index()
76 swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000); in rtw8821c_get_swing_index()
77 for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) { in rtw8821c_get_swing_index()
97 dm_info->delta_power_index[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
98 dm_info->delta_power_index_last[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
108 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); in rtw8821c_phy_bf_init()
140 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8821c_phy_set_param()
141 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); in rtw8821c_phy_set_param()
142 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); in rtw8821c_phy_set_param()
143 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); in rtw8821c_phy_set_param()
147 rtwdev->chip->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); in rtw8821c_phy_set_param()
152 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; in rtw8821c_phy_set_param()
168 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); in rtw8821c_mac_init()
184 rtw_write16(rtwdev, REG_TXPAUSE, 0); in rtw8821c_mac_init()
209 rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40); in rtw8821c_mac_init()
215 return 0; in rtw8821c_mac_init()
231 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); in rtw8821c_set_channel_rf()
260 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); in rtw8821c_set_channel_rf()
261 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf); in rtw8821c_set_channel_rf()
263 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); in rtw8821c_set_channel_rf()
266 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); in rtw8821c_set_channel_rf()
268 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8821c_set_channel_rf()
276 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
277 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
278 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
279 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
282 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
283 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); in rtw8821c_set_channel_rxdfir()
284 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
285 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
288 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
289 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
290 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
291 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
301 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8821c_set_channel_bb()
302 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); in rtw8821c_set_channel_bb()
303 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); in rtw8821c_set_channel_bb()
304 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); in rtw8821c_set_channel_bb()
306 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0); in rtw8821c_set_channel_bb()
307 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); in rtw8821c_set_channel_bb()
309 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); in rtw8821c_set_channel_bb()
310 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); in rtw8821c_set_channel_bb()
311 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); in rtw8821c_set_channel_bb()
314 rtwdev->chip->ch_param[0]); in rtw8821c_set_channel_bb()
321 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); in rtw8821c_set_channel_bb()
322 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); in rtw8821c_set_channel_bb()
323 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8821c_set_channel_bb()
324 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); in rtw8821c_set_channel_bb()
327 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1); in rtw8821c_set_channel_bb()
329 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2); in rtw8821c_set_channel_bb()
331 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3); in rtw8821c_set_channel_bb()
334 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); in rtw8821c_set_channel_bb()
336 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); in rtw8821c_set_channel_bb()
338 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); in rtw8821c_set_channel_bb()
340 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); in rtw8821c_set_channel_bb()
347 val32 &= 0xffcffc00; in rtw8821c_set_channel_bb()
348 val32 |= 0x10010000; in rtw8821c_set_channel_bb()
351 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
360 val32 &= 0xff3ff300; in rtw8821c_set_channel_bb()
361 val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) | in rtw8821c_set_channel_bb()
365 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
369 val32 &= 0xfcffcf00; in rtw8821c_set_channel_bb()
370 val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) | in rtw8821c_set_channel_bb()
374 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
378 val32 &= 0xefcefc00; in rtw8821c_set_channel_bb()
379 val32 |= 0x200240; in rtw8821c_set_channel_bb()
382 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
383 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
387 val32 &= 0xefcefc00; in rtw8821c_set_channel_bb()
388 val32 |= 0x300380; in rtw8821c_set_channel_bb()
391 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
392 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
401 u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6}; in rtw8821c_get_bb_swing()
406 tx_bb_swing = 0; in rtw8821c_get_bb_swing()
474 page = *phy_status & 0xf; in query_phy_status()
477 case 0: in query_phy_status()
497 memset(pkt_stat, 0, sizeof(*pkt_stat)); in rtw8821c_query_rx_desc()
533 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; in rtw8821c_set_tx_power_index_by_rate()
538 for (j = 0; j < rtw_rate_size[rs]; j++) { in rtw8821c_set_tx_power_index_by_rate()
541 shift = rate & 0x3; in rtw8821c_set_tx_power_index_by_rate()
543 if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) { in rtw8821c_set_tx_power_index_by_rate()
544 rate_idx = rate & 0xfc; in rtw8821c_set_tx_power_index_by_rate()
547 phy_pwr_idx = 0; in rtw8821c_set_tx_power_index_by_rate()
557 for (path = 0; path < hal->rf_path_num; path++) { in rtw8821c_set_tx_power_index()
558 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { in rtw8821c_set_tx_power_index()
587 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
591 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
595 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
599 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
607 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); in rtw8821c_false_alarm_statistics()
615 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
616 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
622 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; in rtw8821c_do_iqk()
632 for (counter = 0; counter < 300; counter++) { in rtw8821c_do_iqk()
634 if (rf_reg == 0xabcde) in rtw8821c_do_iqk()
638 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); in rtw8821c_do_iqk()
641 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); in rtw8821c_do_iqk()
643 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", in rtw8821c_do_iqk()
689 u8 regval = 0; in rtw8821c_coex_cfg_ant_switch()
712 if (coex_rfe->rfe_module_type != 0x4 && in rtw8821c_coex_cfg_ant_switch()
713 coex_rfe->rfe_module_type != 0x2) in rtw8821c_coex_cfg_ant_switch()
714 regval = 0x3; in rtw8821c_coex_cfg_ant_switch()
716 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8821c_coex_cfg_ant_switch()
718 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8821c_coex_cfg_ant_switch()
720 regval = (!polarity_inverse ? 0x1 : 0x2); in rtw8821c_coex_cfg_ant_switch()
733 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8821c_coex_cfg_ant_switch()
746 regval = (!polarity_inverse ? 0x0 : 0x1); in rtw8821c_coex_cfg_ant_switch()
789 coex_rfe->ant_switch_polarity = 0; in rtw8821c_coex_cfg_rfe_type()
794 case 0: in rtw8821c_coex_cfg_rfe_type()
851 u8 swing_lower_bound = 0; in rtw8821c_txagc_swing_offset()
852 u8 max_pwr_idx_offset = 0xf; in rtw8821c_txagc_swing_offset()
853 s8 agc_index = 0; in rtw8821c_txagc_swing_offset()
859 if (delta_pwr_idx >= 0) { in rtw8821c_txagc_swing_offset()
869 } else if (delta_pwr_idx < 0) { in rtw8821c_txagc_swing_offset()
924 pwr_idx_offset_lower = 0 - tx_pwr_idx; in rtw8821c_pwrtrack_set()
937 if (rtwdev->efuse.thermal_meter[0] == 0xff) in rtw8821c_phy_pwrtrack()
940 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); in rtw8821c_phy_pwrtrack()
975 if (efuse->power_track_type != 0) in rtw8821c_pwr_track()
980 GENMASK(17, 16), 0x03); in rtw8821c_pwr_track()
1027 pd[4] = 0x1d; in rtw8821c_phy_cck_pd_set()
1038 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); in rtw8821c_phy_cck_pd_set()
1039 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, in rtw8821c_phy_cck_pd_set()
1044 {0x0086,
1048 RTW_PWR_CMD_WRITE, BIT(0), 0},
1049 {0x0086,
1054 {0x004A,
1058 RTW_PWR_CMD_WRITE, BIT(0), 0},
1059 {0x0005,
1063 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1064 {0x0300,
1068 RTW_PWR_CMD_WRITE, 0xFF, 0},
1069 {0x0301,
1073 RTW_PWR_CMD_WRITE, 0xFF, 0},
1074 {0xFFFF,
1077 0,
1078 RTW_PWR_CMD_END, 0, 0},
1082 {0x0020,
1086 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1087 {0x0001,
1092 {0x0000,
1096 RTW_PWR_CMD_WRITE, BIT(5), 0},
1097 {0x0005,
1101 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1102 {0x0075,
1106 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1107 {0x0006,
1112 {0x0075,
1116 RTW_PWR_CMD_WRITE, BIT(0), 0},
1117 {0x0006,
1121 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1122 {0x0005,
1126 RTW_PWR_CMD_WRITE, BIT(7), 0},
1127 {0x0005,
1131 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1132 {0x10C3,
1136 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1137 {0x0005,
1141 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1142 {0x0005,
1146 RTW_PWR_CMD_POLLING, BIT(0), 0},
1147 {0x0020,
1152 {0x0074,
1157 {0x0022,
1161 RTW_PWR_CMD_WRITE, BIT(1), 0},
1162 {0x0062,
1168 {0x0061,
1172 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1173 {0x007C,
1177 RTW_PWR_CMD_WRITE, BIT(1), 0},
1178 {0xFFFF,
1181 0,
1182 RTW_PWR_CMD_END, 0, 0},
1186 {0x0093,
1190 RTW_PWR_CMD_WRITE, BIT(3), 0},
1191 {0x001F,
1195 RTW_PWR_CMD_WRITE, 0xFF, 0},
1196 {0x0049,
1200 RTW_PWR_CMD_WRITE, BIT(1), 0},
1201 {0x0006,
1205 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1206 {0x0002,
1210 RTW_PWR_CMD_WRITE, BIT(1), 0},
1211 {0x10C3,
1215 RTW_PWR_CMD_WRITE, BIT(0), 0},
1216 {0x0005,
1221 {0x0005,
1225 RTW_PWR_CMD_POLLING, BIT(1), 0},
1226 {0x0020,
1230 RTW_PWR_CMD_WRITE, BIT(3), 0},
1231 {0x0000,
1236 {0xFFFF,
1239 0,
1240 RTW_PWR_CMD_END, 0, 0},
1244 {0x0007,
1248 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1249 {0x0067,
1253 RTW_PWR_CMD_WRITE, BIT(5), 0},
1254 {0x0005,
1259 {0x004A,
1263 RTW_PWR_CMD_WRITE, BIT(0), 0},
1264 {0x0067,
1268 RTW_PWR_CMD_WRITE, BIT(5), 0},
1269 {0x0067,
1273 RTW_PWR_CMD_WRITE, BIT(4), 0},
1274 {0x004F,
1278 RTW_PWR_CMD_WRITE, BIT(0), 0},
1279 {0x0067,
1283 RTW_PWR_CMD_WRITE, BIT(1), 0},
1284 {0x0046,
1289 {0x0067,
1293 RTW_PWR_CMD_WRITE, BIT(2), 0},
1294 {0x0046,
1299 {0x0062,
1304 {0x0081,
1308 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1309 {0x0005,
1314 {0x0086,
1318 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1319 {0x0086,
1323 RTW_PWR_CMD_POLLING, BIT(1), 0},
1324 {0x0090,
1328 RTW_PWR_CMD_WRITE, BIT(1), 0},
1329 {0x0044,
1333 RTW_PWR_CMD_WRITE, 0xFF, 0},
1334 {0x0040,
1338 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1339 {0x0041,
1343 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1344 {0x0042,
1348 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1349 {0xFFFF,
1352 0,
1353 RTW_PWR_CMD_END, 0, 0},
1369 {0xFFFF, 0x00,
1376 {0xFFFF, 0x0000,
1383 {0x0009, 0x6380,
1387 {0xFFFF, 0x0000,
1394 {0xFFFF, 0x0000,
1412 [0] = RTW_DEF_RFE(8821c, 0, 0),
1416 [0] = { .addr = 0xc50, .mask = 0x7f },
1426 /* not sure what [0] stands for */
1429 {16, 16, 0, 0, 1},
1430 {16, 16, 16, 0, 1},
1435 /* not sure what [0] stands for */
1503 {0x55555555, 0x55555555}, /* case-0 */
1504 {0x55555555, 0x55555555},
1505 {0x66555555, 0x66555555},
1506 {0xaaaaaaaa, 0xaaaaaaaa},
1507 {0x5a5a5a5a, 0x5a5a5a5a},
1508 {0xfafafafa, 0xfafafafa}, /* case-5 */
1509 {0x6a5a5555, 0xaaaaaaaa},
1510 {0x6a5a56aa, 0x6a5a56aa},
1511 {0x6a5a5a5a, 0x6a5a5a5a},
1512 {0x66555555, 0x5a5a5a5a},
1513 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1514 {0x66555555, 0xaaaaaaaa},
1515 {0x66555555, 0x6a5a5aaa},
1516 {0x66555555, 0x6aaa6aaa},
1517 {0x66555555, 0x6a5a5aaa},
1518 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1519 {0xffff55ff, 0xfafafafa},
1520 {0xffff55ff, 0x6afa5afa},
1521 {0xaaffffaa, 0xfafafafa},
1522 {0xaa5555aa, 0x5a5a5a5a},
1523 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1524 {0xaa5555aa, 0xaaaaaaaa},
1525 {0xffffffff, 0x55555555},
1526 {0xffffffff, 0x5a5a5a5a},
1527 {0xffffffff, 0x5a5a5a5a},
1528 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1529 {0x55555555, 0x5a5a5a5a},
1530 {0x55555555, 0xaaaaaaaa},
1531 {0x66555555, 0x6a5a6a5a},
1532 {0x66556655, 0x66556655},
1533 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1534 {0xffffffff, 0x5aaa5aaa},
1535 {0x56555555, 0x5a5a5aaa}
1540 {0xffffffff, 0xffffffff}, /* case-100 */
1541 {0xffff55ff, 0xfafafafa},
1542 {0x66555555, 0x66555555},
1543 {0xaaaaaaaa, 0xaaaaaaaa},
1544 {0x5a5a5a5a, 0x5a5a5a5a},
1545 {0xffffffff, 0xffffffff}, /* case-105 */
1546 {0x5afa5afa, 0x5afa5afa},
1547 {0x55555555, 0xfafafafa},
1548 {0x66555555, 0xfafafafa},
1549 {0x66555555, 0x5a5a5a5a},
1550 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1551 {0x66555555, 0xaaaaaaaa},
1552 {0xffff55ff, 0xfafafafa},
1553 {0xffff55ff, 0x5afa5afa},
1554 {0xffff55ff, 0xaaaaaaaa},
1555 {0xffff55ff, 0xffff55ff}, /* case-115 */
1556 {0xaaffffaa, 0x5afa5afa},
1557 {0xaaffffaa, 0xaaaaaaaa},
1558 {0xffffffff, 0xfafafafa},
1559 {0xffff55ff, 0xfafafafa},
1560 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1561 {0xffff55ff, 0x5afa5afa},
1562 {0xffff55ff, 0x5afa5afa},
1563 {0x55ff55ff, 0x55ff55ff}
1568 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1569 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1570 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1571 { {0x61, 0x35, 0x03, 0x11, 0x11} },
1572 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1573 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1574 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1575 { {0x61, 0x35, 0x03, 0x11, 0x10} },
1576 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1577 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1578 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1579 { {0x61, 0x08, 0x03, 0x11, 0x15} },
1580 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1581 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1582 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1583 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1584 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1585 { {0x51, 0x3a, 0x03, 0x11, 0x50} },
1586 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1587 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1588 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1589 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
1590 { {0x51, 0x08, 0x03, 0x30, 0x54} },
1591 { {0x55, 0x08, 0x03, 0x10, 0x54} },
1592 { {0x65, 0x10, 0x03, 0x11, 0x10} },
1593 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1594 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1595 { {0x61, 0x08, 0x03, 0x11, 0x11} }
1600 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1601 { {0x61, 0x45, 0x03, 0x11, 0x11} },
1602 { {0x61, 0x25, 0x03, 0x11, 0x11} },
1603 { {0x61, 0x35, 0x03, 0x11, 0x11} },
1604 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1605 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1606 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1607 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1608 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1609 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1610 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1611 { {0x61, 0x10, 0x03, 0x11, 0x11} },
1612 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1613 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1614 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1615 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1616 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1617 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1618 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1619 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1620 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1621 { {0x51, 0x10, 0x03, 0x10, 0x50} }
1624 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} };
1628 {0, 0, false, 7}, /* for normal */
1629 {0, 20, false, 7}, /* for WL-CPT */
1637 {0, 0, false, 7}, /* for normal */
1638 {0, 20, false, 7}, /* for WL-CPT */
1642 {0, 28, true, 5}
1648 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1650 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1652 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1657 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1659 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1661 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1666 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1668 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1670 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1675 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1677 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1679 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1684 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1689 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1694 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1699 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1704 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1709 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1714 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1719 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1724 .pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0],
1727 .pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0],
1730 .pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0],
1733 .pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0],
1747 {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1748 {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1749 {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1750 {0, 0, RTW_REG_DOMAIN_NL},
1751 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1752 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1753 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1754 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1755 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1756 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1757 {0, 0, RTW_REG_DOMAIN_NL},
1758 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1759 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1760 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1761 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1762 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A},
1763 {0, 0, RTW_REG_DOMAIN_NL},
1764 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1765 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1766 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1767 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1768 {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1787 .max_power_index = 0x3f,
1788 .csi_buf_pg_num = 0,
1791 .dig_min = 0x1c,
1795 .sys_func_en = 0xD8,
1803 .rf_base_addr = {0x2800, 0x2c00},
1804 .rf_sipi_addr = {0xc90, 0xe90},
1818 .coex_para_ver = 0x19092746,
1819 .bt_desired_ver = 0x46,
1839 .bt_afh_span_bw20 = 0x24,
1840 .bt_afh_span_bw40 = 0x36,