Lines Matching full:bit
302 #define RXDMA_AGG_EN BIT(7)
306 /* Regsiter Bit and Content definition */
308 #define ISO_MD2PP BIT(0)
309 #define ISO_PA2PCIE BIT(3)
310 #define ISO_PLL2MD BIT(4)
311 #define ISO_PWC_DV2RP BIT(11)
312 #define ISO_PWC_RV2RP BIT(12)
315 #define FEN_MREGEN BIT(15)
316 #define FEN_DCORE BIT(11)
317 #define FEN_CPUEN BIT(10)
319 #define PAD_HWPD_IDN BIT(22)
321 #define SYS_CLKSEL_80M BIT(0)
322 #define SYS_PS_CLKSEL BIT(1)
323 #define SYS_CPU_CLKSEL BIT(2)
324 #define SYS_MAC_CLK_EN BIT(11)
325 #define SYS_SWHW_SEL BIT(14)
326 #define SYS_FWHW_SEL BIT(15)
328 #define CMDEEPROM_EN BIT(5)
329 #define CMDEERPOMSEL BIT(4)
330 #define CMD9346CR_9356SEL BIT(4)
332 #define AFE_MBEN BIT(1)
333 #define AFE_BGEN BIT(0)
335 #define SPS1_SWEN BIT(1)
336 #define SPS1_LDEN BIT(0)
338 #define RF_EN BIT(0)
339 #define RF_RSTB BIT(1)
340 #define RF_SDMRSTB BIT(2)
342 #define LDA15_EN BIT(0)
344 #define LDV12_EN BIT(0)
345 #define LDV12_SDBY BIT(1)
347 #define XTAL_GATE_AFE BIT(10)
349 #define APLL_EN BIT(0)
351 #define AFR_CARDBEN BIT(0)
352 #define AFR_CLKRUN_SEL BIT(1)
353 #define AFR_FUNCREGEN BIT(2)
355 #define APSDOFF_STATUS BIT(15)
356 #define APSDOFF BIT(14)
357 #define BBRSTN BIT(13)
358 #define BB_GLB_RSTN BIT(12)
359 #define SCHEDULE_EN BIT(10)
360 #define MACRXEN BIT(9)
361 #define MACTXEN BIT(8)
362 #define DDMA_EN BIT(7)
363 #define FW2HW_EN BIT(6)
364 #define RXDMA_EN BIT(5)
365 #define TXDMA_EN BIT(4)
366 #define HCI_RXDMA_EN BIT(3)
367 #define HCI_TXDMA_EN BIT(2)
369 #define STOPHCCA BIT(6)
370 #define STOPHIGH BIT(5)
371 #define STOPMGT BIT(4)
372 #define STOPVO BIT(3)
373 #define STOPVI BIT(2)
374 #define STOPBE BIT(1)
375 #define STOPBK BIT(0)
378 #define LBK_MAC_LB (BIT(0) | BIT(1) | BIT(3))
379 #define LBK_MAC_DLB (BIT(0) | BIT(1))
380 #define LBK_DMA_LB (BIT(0) | BIT(1) | BIT(2))
382 #define TCP_OFDL_EN BIT(25)
383 #define HWPC_TX_EN BIT(24)
384 #define TXDMAPRE2FULL BIT(23)
385 #define DISCW BIT(20)
386 #define TCRICV BIT(19)
387 #define cfendform BIT(17)
388 #define TCRCRC BIT(16)
389 #define FAKE_IMEM_EN BIT(15)
390 #define TSFRST BIT(9)
391 #define TSFEN BIT(8)
392 #define FWALLRDY (BIT(0) | BIT(1) | BIT(2) | \
393 BIT(3) | BIT(4) | BIT(5) | \
394 BIT(6) | BIT(7))
395 #define FWRDY BIT(7)
396 #define BASECHG BIT(6)
397 #define IMEM BIT(5)
398 #define DMEM_CODE_DONE BIT(4)
399 #define EXT_IMEM_CHK_RPT BIT(3)
400 #define EXT_IMEM_CODE_DONE BIT(2)
401 #define IMEM_CHK_RPT BIT(1)
402 #define IMEM_CODE_DONE BIT(0)
403 #define EMEM_CODE_DONE BIT(2)
404 #define EMEM_CHK_RPT BIT(3)
405 #define IMEM_RDY BIT(5)
414 #define TCR_TSFEN BIT(8)
415 #define TCR_TSFRST BIT(9)
416 #define TCR_FAKE_IMEM_EN BIT(15)
417 #define TCR_CRC BIT(16)
418 #define TCR_ICV BIT(19)
419 #define TCR_DISCW BIT(20)
420 #define TCR_HWPC_TX_EN BIT(24)
421 #define TCR_TCP_OFDL_EN BIT(25)
425 #define RCR_APPFCS BIT(31)
426 #define RCR_DIS_ENC_2BYTE BIT(30)
427 #define RCR_DIS_AES_2BYTE BIT(29)
428 #define RCR_HTC_LOC_CTRL BIT(28)
429 #define RCR_ENMBID BIT(27)
430 #define RCR_RX_TCPOFDL_EN BIT(26)
431 #define RCR_APP_PHYST_RXFF BIT(25)
432 #define RCR_APP_PHYST_STAFF BIT(24)
433 #define RCR_CBSSID BIT(23)
434 #define RCR_APWRMGT BIT(22)
435 #define RCR_ADD3 BIT(21)
436 #define RCR_AMF BIT(20)
437 #define RCR_ACF BIT(19)
438 #define RCR_ADF BIT(18)
439 #define RCR_APP_MIC BIT(17)
440 #define RCR_APP_ICV BIT(16)
441 #define RCR_RXFTH BIT(13)
442 #define RCR_AICV BIT(12)
443 #define RCR_RXDESC_LK_EN BIT(11)
444 #define RCR_APP_BA_SSN BIT(6)
445 #define RCR_ACRC32 BIT(5)
446 #define RCR_RXSHFT_EN BIT(4)
447 #define RCR_AB BIT(3)
448 #define RCR_AM BIT(2)
449 #define RCR_APM BIT(1)
450 #define RCR_AAP BIT(0)
466 #define ENUART BIT(7)
467 #define ENJTAG BIT(3)
468 #define BTMODE (BIT(2) | BIT(1))
469 #define ENBT BIT(0)
471 #define ENMBID BIT(7)
472 #define BCNUM (BIT(6) | BIT(5) | BIT(4))
480 #define ENSWBCN BIT(15)
492 #define RRSR_1M BIT(0)
493 #define RRSR_2M BIT(1)
494 #define RRSR_5_5M BIT(2)
495 #define RRSR_11M BIT(3)
496 #define RRSR_6M BIT(4)
497 #define RRSR_9M BIT(5)
498 #define RRSR_12M BIT(6)
499 #define RRSR_18M BIT(7)
500 #define RRSR_24M BIT(8)
501 #define RRSR_36M BIT(9)
502 #define RRSR_48M BIT(10)
503 #define RRSR_54M BIT(11)
504 #define RRSR_MCS0 BIT(12)
505 #define RRSR_MCS1 BIT(13)
506 #define RRSR_MCS2 BIT(14)
507 #define RRSR_MCS3 BIT(15)
508 #define RRSR_MCS4 BIT(16)
509 #define RRSR_MCS5 BIT(17)
510 #define RRSR_MCS6 BIT(18)
511 #define RRSR_MCS7 BIT(19)
512 #define BRSR_ACKSHORTPMB BIT(23)
563 #define ACMHW_HWEN BIT(0)
564 #define ACMHW_BEQEN BIT(1)
565 #define ACMHW_VIQEN BIT(2)
566 #define ACMHW_VOQEN BIT(3)
567 #define ACMHW_BEQSTATUS BIT(4)
568 #define ACMHW_VIQSTATUS BIT(5)
569 #define ACMHW_VOQSTATUS BIT(6)
574 #define NAV_UPPER_EN BIT(16)
578 #define BW_OPMODE_20MHZ BIT(2)
579 #define BW_OPMODE_5G BIT(1)
580 #define BW_OPMODE_11J BIT(0)
582 #define RXERR_RPT_RST BIT(27)
598 #define SCR_TXUSEDK BIT(0)
599 #define SCR_RXUSEDK BIT(1)
600 #define SCR_TXENCENABLE BIT(2)
601 #define SCR_RXENCENABLE BIT(3)
602 #define SCR_SKBYA2 BIT(4)
603 #define SCR_NOSKMC BIT(5)
605 #define CAM_VALID BIT(15)
607 #define CAM_USEDK BIT(5)
618 #define CAM_WRITE BIT(16)
620 #define CAM_POLLINIG BIT(31)
622 #define WOW_PMEN BIT(0)
623 #define WOW_WOMEN BIT(1)
624 #define WOW_MAGIC BIT(2)
625 #define WOW_UWF BIT(3)
627 #define GPIOMUX_EN BIT(3)
632 #define GPIOSEL_GPIO_MASK (~(BIT(0)|BIT(1)))
634 #define HST_RDBUSY BIT(0)
635 #define CPU_WTBUSY BIT(1)
638 #define IMR_CPUERR BIT(5)
639 #define IMR_ATIMEND BIT(4)
640 #define IMR_TBDOK BIT(3)
641 #define IMR_TBDER BIT(2)
642 #define IMR_BCNDMAINT8 BIT(1)
643 #define IMR_BCNDMAINT7 BIT(0)
644 #define IMR_BCNDMAINT6 BIT(31)
645 #define IMR_BCNDMAINT5 BIT(30)
646 #define IMR_BCNDMAINT4 BIT(29)
647 #define IMR_BCNDMAINT3 BIT(28)
648 #define IMR_BCNDMAINT2 BIT(27)
649 #define IMR_BCNDMAINT1 BIT(26)
650 #define IMR_BCNDOK8 BIT(25)
651 #define IMR_BCNDOK7 BIT(24)
652 #define IMR_BCNDOK6 BIT(23)
653 #define IMR_BCNDOK5 BIT(22)
654 #define IMR_BCNDOK4 BIT(21)
655 #define IMR_BCNDOK3 BIT(20)
656 #define IMR_BCNDOK2 BIT(19)
657 #define IMR_BCNDOK1 BIT(18)
658 #define IMR_TIMEOUT2 BIT(17)
659 #define IMR_TIMEOUT1 BIT(16)
660 #define IMR_TXFOVW BIT(15)
661 #define IMR_PSTIMEOUT BIT(14)
662 #define IMR_BCNINT BIT(13)
663 #define IMR_RXFOVW BIT(12)
664 #define IMR_RDU BIT(11)
665 #define IMR_RXCMDOK BIT(10)
666 #define IMR_BDOK BIT(9)
667 #define IMR_HIGHDOK BIT(8)
668 #define IMR_COMDOK BIT(7)
669 #define IMR_MGNTDOK BIT(6)
670 #define IMR_HCCADOK BIT(5)
671 #define IMR_BKDOK BIT(4)
672 #define IMR_BEDOK BIT(3)
673 #define IMR_VIDOK BIT(2)
674 #define IMR_VODOK BIT(1)
675 #define IMR_ROK BIT(0)
677 #define TPPOLL_BKQ BIT(0)
678 #define TPPOLL_BEQ BIT(1)
679 #define TPPOLL_VIQ BIT(2)
680 #define TPPOLL_VOQ BIT(3)
681 #define TPPOLL_BQ BIT(4)
682 #define TPPOLL_CQ BIT(5)
683 #define TPPOLL_MQ BIT(6)
684 #define TPPOLL_HQ BIT(7)
685 #define TPPOLL_HCCAQ BIT(8)
686 #define TPPOLL_STOPBK BIT(9)
687 #define TPPOLL_STOPBE BIT(10)
688 #define TPPOLL_STOPVI BIT(11)
689 #define TPPOLL_STOPVO BIT(12)
690 #define TPPOLL_STOPMGT BIT(13)
691 #define TPPOLL_STOPHIGH BIT(14)
692 #define TPPOLL_STOPHCCA BIT(15)
695 #define CCX_CMD_CLM_ENABLE BIT(0)
696 #define CCX_CMD_NHM_ENABLE BIT(1)
697 #define CCX_CMD_FUNCTION_ENABLE BIT(8)
698 #define CCX_CMD_IGNORE_CCA BIT(9)
699 #define CCX_CMD_IGNORE_TXON BIT(10)
700 #define CCX_CLM_RESULT_READY BIT(16)
701 #define CCX_NHM_RESULT_READY BIT(16)
820 #define RCR_9356SEL BIT(6)
824 #define TCR_SAT BIT(24)
827 #define RCR_ONLYERLPKT BIT(31)
855 #define HAL_8192S_HW_GPIO_OFF_BIT BIT(3)
857 #define HAL_8192S_HW_GPIO_WPS_BIT BIT(4)