Lines Matching full:bit
10 #define SYS_ISO_MD2PP BIT(0)
11 #define SYS_ISO_ANALOG_IPS BIT(5)
12 #define SYS_ISO_DIOR BIT(9)
13 #define SYS_ISO_PWC_EV25V BIT(14)
14 #define SYS_ISO_PWC_EV12V BIT(15)
17 #define SYS_FUNC_BBRSTB BIT(0)
18 #define SYS_FUNC_BB_GLB_RSTN BIT(1)
19 #define SYS_FUNC_USBA BIT(2)
20 #define SYS_FUNC_UPLL BIT(3)
21 #define SYS_FUNC_USBD BIT(4)
22 #define SYS_FUNC_DIO_PCIE BIT(5)
23 #define SYS_FUNC_PCIEA BIT(6)
24 #define SYS_FUNC_PPLL BIT(7)
25 #define SYS_FUNC_PCIED BIT(8)
26 #define SYS_FUNC_DIOE BIT(9)
27 #define SYS_FUNC_CPU_ENABLE BIT(10)
28 #define SYS_FUNC_DCORE BIT(11)
29 #define SYS_FUNC_ELDR BIT(12)
30 #define SYS_FUNC_DIO_RF BIT(13)
31 #define SYS_FUNC_HWPDN BIT(14)
32 #define SYS_FUNC_MREGEN BIT(15)
35 #define APS_FSMCO_PFM_ALDN BIT(1)
36 #define APS_FSMCO_PFM_WOWL BIT(3)
37 #define APS_FSMCO_ENABLE_POWERDOWN BIT(4)
38 #define APS_FSMCO_MAC_ENABLE BIT(8)
39 #define APS_FSMCO_MAC_OFF BIT(9)
40 #define APS_FSMCO_SW_LPS BIT(10)
41 #define APS_FSMCO_HW_SUSPEND BIT(11)
42 #define APS_FSMCO_PCIE BIT(12)
43 #define APS_FSMCO_HW_POWERDOWN BIT(15)
44 #define APS_FSMCO_WLON_RESET BIT(16)
47 #define SYS_CLK_ANAD16V_ENABLE BIT(0)
48 #define SYS_CLK_ANA8M BIT(1)
49 #define SYS_CLK_MACSLP BIT(4)
50 #define SYS_CLK_LOADER_ENABLE BIT(5)
51 #define SYS_CLK_80M_SSC_DISABLE BIT(7)
52 #define SYS_CLK_80M_SSC_ENABLE_HO BIT(8)
53 #define SYS_CLK_PHY_SSC_RSTB BIT(9)
54 #define SYS_CLK_SEC_CLK_ENABLE BIT(10)
55 #define SYS_CLK_MAC_CLK_ENABLE BIT(11)
56 #define SYS_CLK_ENABLE BIT(12)
57 #define SYS_CLK_RING_CLK_ENABLE BIT(13)
60 #define EEPROM_BOOT BIT(4)
61 #define EEPROM_ENABLE BIT(5)
65 #define AFE_MISC_WL_XTAL_CTRL BIT(6)
73 #define RF_ENABLE BIT(0)
74 #define RF_RSTB BIT(1)
75 #define RF_SDMRSTB BIT(2)
78 #define LDOA15_ENABLE BIT(0)
79 #define LDOA15_STANDBY BIT(1)
80 #define LDOA15_OBUF BIT(2)
81 #define LDOA15_REG_VOS BIT(3)
85 #define LDOV12D_ENABLE BIT(0)
86 #define LDOV12D_STANDBY BIT(1)
92 #define LPLDO_HSM BIT(2)
93 #define LPLDO_LSM_DIS BIT(3)
96 #define AFE_XTAL_ENABLE BIT(0)
97 #define AFE_XTAL_B_SELECT BIT(1)
98 #define AFE_XTAL_GATE_USB BIT(8)
99 #define AFE_XTAL_GATE_AFE BIT(11)
100 #define AFE_XTAL_RF_GATE BIT(14)
101 #define AFE_XTAL_GATE_DIG BIT(17)
102 #define AFE_XTAL_BT_GATE BIT(20)
108 #define AFE_PLL_ENABLE BIT(0)
109 #define AFE_PLL_320_ENABLE BIT(1)
110 #define APE_PLL_FREF_SELECT BIT(2)
111 #define AFE_PLL_EDGE_SELECT BIT(3)
112 #define AFE_PLL_WDOGB BIT(4)
113 #define AFE_PLL_LPF_ENABLE BIT(5)
119 #define EFUSE_TRPT BIT(7)
121 #define EFUSE_CELL_SEL (BIT(8) | BIT(9))
122 #define EFUSE_LDOE25_ENABLE BIT(31)
133 #define PWR_DATA_EEPRPAD_RFE_CTRL_EN BIT(11)
142 #define GPIO_INTM_EDGE_TRIG_IRQ BIT(9)
145 #define LEDCFG0_DPDT_SELECT BIT(23)
148 #define LEDCFG2_DPDT_SELECT BIT(7)
159 #define GPIO_IO_SEL_2_GPIO09_INPUT BIT(1)
160 #define GPIO_IO_SEL_2_GPIO09_IRQ BIT(9)
164 #define PAD_CTRL1_SW_DPDT_SEL_DATA BIT(0)
169 #define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW
171 #define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity
173 #define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */
175 #define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW
177 #define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW
179 #define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity
181 #define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */
182 #define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS
184 #define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW
186 #define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity
188 #define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */
194 #define MCU_FW_DL_ENABLE BIT(0)
195 #define MCU_FW_DL_READY BIT(1)
196 #define MCU_FW_DL_CSUM_REPORT BIT(2)
197 #define MCU_MAC_INIT_READY BIT(3)
198 #define MCU_BB_INIT_READY BIT(4)
199 #define MCU_RF_INIT_READY BIT(5)
200 #define MCU_WINT_INIT_READY BIT(6)
201 #define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */
202 #define MCU_CP_RESET BIT(23)
211 #define IMR0_TXCCK BIT(30) /* TXRPT interrupt when CCX bit
213 #define IMR0_PSTIMEOUT BIT(29) /* Power Save Time Out Int */
214 #define IMR0_GTINT4 BIT(28) /* Set when GTIMER4 expires */
215 #define IMR0_GTINT3 BIT(27) /* Set when GTIMER3 expires */
216 #define IMR0_TBDER BIT(26) /* Transmit Beacon0 Error */
217 #define IMR0_TBDOK BIT(25) /* Transmit Beacon0 OK */
218 #define IMR0_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle
220 #define IMR0_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */
221 #define IMR0_BCNDERR0 BIT(16) /* Beacon Queue DMA Error 0 */
222 #define IMR0_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR &
224 #define IMR0_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt
226 #define IMR0_ATIMEND BIT(12) /* CTWidnow End or
228 #define IMR0_HISR1_IND_INT BIT(11) /* HISR1 Indicator
230 #define IMR0_C2HCMD BIT(10) /* CPU to Host Command INT
232 #define IMR0_CPWM2 BIT(9) /* CPU power Mode exchange INT
234 #define IMR0_CPWM BIT(8) /* CPU power Mode exchange INT
236 #define IMR0_HIGHDOK BIT(7) /* High Queue DMA OK */
237 #define IMR0_MGNTDOK BIT(6) /* Management Queue DMA OK */
238 #define IMR0_BKDOK BIT(5) /* AC_BK DMA OK */
239 #define IMR0_BEDOK BIT(4) /* AC_BE DMA OK */
240 #define IMR0_VIDOK BIT(3) /* AC_VI DMA OK */
241 #define IMR0_VODOK BIT(2) /* AC_VO DMA OK */
242 #define IMR0_RDU BIT(1) /* Rx Descriptor Unavailable */
243 #define IMR0_ROK BIT(0) /* Receive DMA OK */
246 #define IMR1_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */
247 #define IMR1_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */
248 #define IMR1_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */
249 #define IMR1_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */
250 #define IMR1_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */
251 #define IMR1_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */
252 #define IMR1_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */
253 #define IMR1_BCNDERR7 BIT(20) /* Beacon Queue DMA Err Int 7 */
254 #define IMR1_BCNDERR6 BIT(19) /* Beacon Queue DMA Err Int 6 */
255 #define IMR1_BCNDERR5 BIT(18) /* Beacon Queue DMA Err Int 5 */
256 #define IMR1_BCNDERR4 BIT(17) /* Beacon Queue DMA Err Int 4 */
257 #define IMR1_BCNDERR3 BIT(16) /* Beacon Queue DMA Err Int 3 */
258 #define IMR1_BCNDERR2 BIT(15) /* Beacon Queue DMA Err Int 2 */
259 #define IMR1_BCNDERR1 BIT(14) /* Beacon Queue DMA Err Int 1 */
260 #define IMR1_ATIMEND_E BIT(13) /* ATIM Window End Extension
262 #define IMR1_TXERR BIT(11) /* Tx Error Flag Int Status,
264 #define IMR1_RXERR BIT(10) /* Rx Error Flag Int Status,
266 #define IMR1_TXFOVW BIT(9) /* Transmit FIFO Overflow */
267 #define IMR1_RXFOVW BIT(8) /* Receive FIFO Overflow */
281 #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23))
282 #define HPON_FSM_BONDING_1T2R BIT(22)
284 #define SYS_CFG_XCLK_VLD BIT(0)
285 #define SYS_CFG_ACLK_VLD BIT(1)
286 #define SYS_CFG_UCLK_VLD BIT(2)
287 #define SYS_CFG_PCLK_VLD BIT(3)
288 #define SYS_CFG_PCIRSTB BIT(4)
289 #define SYS_CFG_V15_VLD BIT(5)
290 #define SYS_CFG_TRP_B15V_EN BIT(7)
291 #define SYS_CFG_SW_OFFLOAD_EN BIT(7) /* For chips with IOL support */
292 #define SYS_CFG_SIC_IDLE BIT(8)
293 #define SYS_CFG_BD_MAC2 BIT(9)
294 #define SYS_CFG_BD_MAC1 BIT(10)
295 #define SYS_CFG_IC_MACPHY_MODE BIT(11)
296 #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15))
297 #define SYS_CFG_BT_FUNC BIT(16)
298 #define SYS_CFG_VENDOR_ID BIT(19)
299 #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19))
301 #define SYS_CFG_VENDOR_ID_SMIC BIT(18)
302 #define SYS_CFG_VENDOR_ID_UMC BIT(19)
303 #define SYS_CFG_PAD_HWPD_IDN BIT(22)
304 #define SYS_CFG_TRP_VAUX_EN BIT(23)
305 #define SYS_CFG_TRP_BT_EN BIT(24)
306 #define SYS_CFG_SPS_LDO_SEL BIT(24) /* 8192eu */
307 #define SYS_CFG_BD_PKG_SEL BIT(25)
308 #define SYS_CFG_BD_HCI_SEL BIT(26)
309 #define SYS_CFG_TYPE_ID BIT(27)
310 #define SYS_CFG_RTL_ID BIT(23) /* TestChip ID,
312 #define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode;
314 #define SYS_CFG_CHIP_VERSION_MASK 0xf000 /* Bit 12 - 15 */
318 #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1))
319 #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3))
320 #define GPIO_HCI_SEL (BIT(4) | BIT(5))
321 #define GPIO_PKG_SEL_HCI BIT(6)
322 #define GPIO_FEN_GPS BIT(7)
323 #define GPIO_FEN_BT BIT(8)
324 #define GPIO_FEN_WL BIT(9)
325 #define GPIO_FEN_PCI BIT(10)
326 #define GPIO_FEN_USB BIT(11)
327 #define GPIO_BTRF_HWPDN_N BIT(12)
328 #define GPIO_WLRF_HWPDN_N BIT(13)
329 #define GPIO_PDN_BT_N BIT(14)
330 #define GPIO_PDN_GPS_N BIT(15)
331 #define GPIO_BT_CTL_HWPDN BIT(16)
332 #define GPIO_GPS_CTL_HWPDN BIT(17)
333 #define GPIO_PPHY_SUSB BIT(20)
334 #define GPIO_UPHY_SUSB BIT(21)
335 #define GPIO_PCI_SUSEN BIT(22)
336 #define GPIO_USB_SUSEN BIT(23)
337 #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
343 #define CR_HCI_TXDMA_ENABLE BIT(0)
344 #define CR_HCI_RXDMA_ENABLE BIT(1)
345 #define CR_TXDMA_ENABLE BIT(2)
346 #define CR_RXDMA_ENABLE BIT(3)
347 #define CR_PROTOCOL_ENABLE BIT(4)
348 #define CR_SCHEDULE_ENABLE BIT(5)
349 #define CR_MAC_TX_ENABLE BIT(6)
350 #define CR_MAC_RX_ENABLE BIT(7)
351 #define CR_SW_BEACON_ENABLE BIT(8)
352 #define CR_SECURITY_ENABLE BIT(9)
353 #define CR_CALTIMER_ENABLE BIT(10)
373 #define TRXDMA_CTRL_RXDMA_AGG_EN BIT(2)
439 #define RQPN_LOAD BIT(31)
444 #define TXDMA_OFFSET_DROP_DATA_EN BIT(9)
451 #define AUTO_LLT_INIT_LLT BIT(16)
461 #define RXDMA_USB_AGG_ENABLE BIT(31)
463 #define RXPKT_NUM_RXDMA_IDLE BIT(17)
464 #define RXPKT_NUM_RW_RELEASE_EN BIT(18)
493 #define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7)
494 #define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12)
519 #define RSR_1M BIT(0)
520 #define RSR_2M BIT(1)
521 #define RSR_5_5M BIT(2)
522 #define RSR_11M BIT(3)
523 #define RSR_6M BIT(4)
524 #define RSR_9M BIT(5)
525 #define RSR_12M BIT(6)
526 #define RSR_18M BIT(7)
527 #define RSR_24M BIT(8)
528 #define RSR_36M BIT(9)
529 #define RSR_48M BIT(10)
530 #define RSR_54M BIT(11)
531 #define RSR_MCS0 BIT(12)
532 #define RSR_MCS1 BIT(13)
533 #define RSR_MCS2 BIT(14)
534 #define RSR_MCS3 BIT(15)
535 #define RSR_MCS4 BIT(16)
536 #define RSR_MCS5 BIT(17)
537 #define RSR_MCS6 BIT(18)
538 #define RSR_MCS7 BIT(19)
539 #define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */
540 #define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */
543 #define RSR_ACK_SHORT_PREAMBLE BIT(23)
591 #define TX_REPORT_CTRL_TIMER_ENABLE BIT(1)
622 #define BEACON_ATIM BIT(0)
623 #define BEACON_CTRL_MBSSID BIT(1)
624 #define BEACON_CTRL_TX_BEACON_RPT BIT(2)
625 #define BEACON_FUNCTION_ENABLE BIT(3)
626 #define BEACON_DISABLE_TSF_UPDATE BIT(4)
630 #define DUAL_TSF_RESET_TSF0 BIT(0)
631 #define DUAL_TSF_RESET_TSF1 BIT(1)
632 #define DUAL_TSF_RESET_P2P BIT(4)
633 #define DUAL_TSF_TX_OK BIT(5)
658 #define ACM_HW_CTRL_BK BIT(0)
659 #define ACM_HW_CTRL_BE BIT(1)
660 #define ACM_HW_CTRL_VI BIT(2)
661 #define ACM_HW_CTRL_VO BIT(3)
678 #define APSD_CTRL_OFF BIT(6)
679 #define APSD_CTRL_OFF_STATUS BIT(7)
681 #define BW_OPMODE_20MHZ BIT(2)
682 #define BW_OPMODE_5G BIT(1)
683 #define BW_OPMODE_11J BIT(0)
689 #define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */
690 #define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */
691 #define RCR_ACCEPT_MCAST BIT(2)
692 #define RCR_ACCEPT_BCAST BIT(3)
693 #define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match
695 #define RCR_ACCEPT_PM BIT(5) /* Accept power management
697 #define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */
698 #define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet
700 #define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */
701 #define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */
702 #define RCR_ACCEPT_DATA_FRAME BIT(11) /* Accept all data pkt or use
704 #define RCR_ACCEPT_CTRL_FRAME BIT(12) /* Accept all control pkt or use
706 #define RCR_ACCEPT_MGMT_FRAME BIT(13) /* Accept all mgmt pkt or use
708 #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */
709 #define RCR_UC_DATA_PKT_INT_ENABLE BIT(16) /* Enable unicast data packet
711 #define RCR_BM_DATA_PKT_INT_ENABLE BIT(17) /* Enable broadcast data packet
713 #define RCR_TIM_PARSER_ENABLE BIT(18) /* Enable RX beacon TIM parser*/
714 #define RCR_MFBEN BIT(22)
715 #define RCR_LSIG_ENABLE BIT(23) /* Enable LSIG TXOP Protection
718 LSIGEN bit is set. */
719 #define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */
720 #define RCR_FORCE_ACK BIT(26)
721 #define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */
722 #define RCR_APPEND_PHYSTAT BIT(28)
723 #define RCR_APPEND_ICV BIT(29)
724 #define RCR_APPEND_MIC BIT(30)
725 #define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */
760 #define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8))
762 #define WMAC_TRXPTCL_CTL_BW_40 BIT(7)
763 #define WMAC_TRXPTCL_CTL_BW_80 BIT(8)
767 #define CAM_CMD_POLLING BIT(31)
768 #define CAM_CMD_WRITE BIT(16)
771 #define CAM_WRITE_VALID BIT(15)
775 #define SEC_CFG_TX_USE_DEFKEY BIT(0)
776 #define SEC_CFG_RX_USE_DEFKEY BIT(1)
777 #define SEC_CFG_TX_SEC_ENABLE BIT(2)
778 #define SEC_CFG_RX_SEC_ENABLE BIT(3)
779 #define SEC_CFG_SKBYA2 BIT(4)
780 #define SEC_CFG_NO_SKMC BIT(5)
781 #define SEC_CFG_TXBC_USE_DEFKEY BIT(6)
782 #define SEC_CFG_RXBC_USE_DEFKEY BIT(7)
793 * RX Filters: each bit corresponds to the numerical value of the subtype.
795 * the RCR_ACCEPT_DATA_FRAME, RCR_ACCEPT_CTRL_FRAME, RCR_ACCEPT_MGMT_FRAME bit
799 * bit 8 (0x100) in REG_RXFLTMAP0 to enable reception.
821 #define BT_CONTROL_BT_GRANT BIT(12)
826 #define FPGA_RF_MODE BIT(0)
827 #define FPGA_RF_MODE_JAPAN BIT(1)
828 #define FPGA_RF_MODE_CCK BIT(24)
829 #define FPGA_RF_MODE_OFDM BIT(25)
832 #define FPGA0_TX_INFO_OFDM_PATH_A BIT(0)
833 #define FPGA0_TX_INFO_OFDM_PATH_B BIT(1)
834 #define FPGA0_TX_INFO_OFDM_PATH_C BIT(2)
835 #define FPGA0_TX_INFO_OFDM_PATH_D BIT(3)
841 #define FPGA0_PS_LOWER_CHANNEL BIT(26)
842 #define FPGA0_PS_UPPER_CHANNEL BIT(27)
845 #define FPGA0_HSSI_PARM1_PI BIT(8)
853 #define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9)
854 #define FPGA0_HSSI_PARM2_EDGE_READ BIT(31)
875 #define FPGA0_INT_OE_ANTENNA_A BIT(8)
876 #define FPGA0_INT_OE_ANTENNA_B BIT(9)
884 #define REG_FPGA0_XA_RF_SW_CTRL 0x0870 /* 16 bit */
885 #define REG_FPGA0_XB_RF_SW_CTRL 0x0872 /* 16 bit */
887 #define REG_FPGA0_XC_RF_SW_CTRL 0x0874 /* 16 bit */
888 #define REG_FPGA0_XD_RF_SW_CTRL 0x0876 /* 16 bit */
889 #define FPGA0_RF_3WIRE_DATA BIT(0)
890 #define FPGA0_RF_3WIRE_CLOC BIT(1)
891 #define FPGA0_RF_3WIRE_LOAD BIT(2)
892 #define FPGA0_RF_3WIRE_RW BIT(3)
894 #define FPGA0_RF_RFENV BIT(4)
895 #define FPGA0_RF_TRSW BIT(5) /* Useless now */
896 #define FPGA0_RF_TRSWB BIT(6)
897 #define FPGA0_RF_ANTSW BIT(8)
898 #define FPGA0_RF_ANTSWB BIT(9)
899 #define FPGA0_RF_PAPE BIT(10)
900 #define FPGA0_RF_PAPE5G BIT(11)
904 #define REG_FPGA0_XA_RF_PARM 0x0878 /* 16 bit */
905 #define REG_FPGA0_XB_RF_PARM 0x087a /* 16 bit */
907 #define REG_FPGA0_XC_RF_PARM 0x087c /* 16 bit */
908 #define REG_FPGA0_XD_RF_PARM 0x087e /* 16 bit */
909 #define FPGA0_RF_PARM_RFA_ENABLE BIT(1)
910 #define FPGA0_RF_PARM_RFB_ENABLE BIT(17)
911 #define FPGA0_RF_PARM_CLK_GATE BIT(31)
915 #define FPGA0_ANALOG2_20MHZ BIT(10)
939 #define CCK0_SIDEBAND BIT(4)
943 #define CCK0_AFE_RX_ANT_AB BIT(24)
945 #define CCK0_AFE_RX_ANT_B (BIT(24) | BIT(26))
952 #define OFDM_RF_PATH_RX_A BIT(0)
953 #define OFDM_RF_PATH_RX_B BIT(1)
954 #define OFDM_RF_PATH_RX_C BIT(2)
955 #define OFDM_RF_PATH_RX_D BIT(3)
957 #define OFDM_RF_PATH_TX_A BIT(4)
958 #define OFDM_RF_PATH_TX_B BIT(5)
959 #define OFDM_RF_PATH_TX_C BIT(6)
960 #define OFDM_RF_PATH_TX_D BIT(7)
972 #define OFDM0_SYNC_PATH_NOTCH_FILTER BIT(1)
1002 #define OFDM_LSTF_PRIME_CH_LOW BIT(10)
1003 #define OFDM_LSTF_PRIME_CH_HIGH BIT(11)
1006 #define OFDM_LSTF_CONTINUE_TX BIT(28)
1007 #define OFDM_LSTF_SINGLE_CARRIER BIT(29)
1008 #define OFDM_LSTF_SINGLE_TONE BIT(30)
1075 #define USB_HIMR_TIMEOUT2 BIT(31)
1076 #define USB_HIMR_TIMEOUT1 BIT(30)
1077 #define USB_HIMR_PSTIMEOUT BIT(29)
1078 #define USB_HIMR_GTINT4 BIT(28)
1079 #define USB_HIMR_GTINT3 BIT(27)
1080 #define USB_HIMR_TXBCNERR BIT(26)
1081 #define USB_HIMR_TXBCNOK BIT(25)
1082 #define USB_HIMR_TSF_BIT32_TOGGLE BIT(24)
1083 #define USB_HIMR_BCNDMAINT3 BIT(23)
1084 #define USB_HIMR_BCNDMAINT2 BIT(22)
1085 #define USB_HIMR_BCNDMAINT1 BIT(21)
1086 #define USB_HIMR_BCNDMAINT0 BIT(20)
1087 #define USB_HIMR_BCNDOK3 BIT(19)
1088 #define USB_HIMR_BCNDOK2 BIT(18)
1089 #define USB_HIMR_BCNDOK1 BIT(17)
1090 #define USB_HIMR_BCNDOK0 BIT(16)
1091 #define USB_HIMR_HSISR_IND BIT(15)
1092 #define USB_HIMR_BCNDMAINT_E BIT(14)
1093 /* RSVD BIT(13) */
1094 #define USB_HIMR_CTW_END BIT(12)
1095 /* RSVD BIT(11) */
1096 #define USB_HIMR_C2HCMD BIT(10)
1097 #define USB_HIMR_CPWM2 BIT(9)
1098 #define USB_HIMR_CPWM BIT(8)
1099 #define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK
1101 #define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK
1103 #define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */
1104 #define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */
1105 #define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */
1106 #define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */
1107 #define USB_HIMR_RDU BIT(1) /* Receive Descriptor
1109 #define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */
1112 #define USB_SPEC_USB_AGG_ENABLE BIT(3) /* Enable USB aggregation */
1113 #define USB_SPEC_INT_BULK_SELECT BIT(4) /* Use interrupt endpoint to
1163 #define MODE_AG_CHANNEL_20MHZ BIT(10)
1164 #define MODE_AG_BW_MASK (BIT(10) | BIT(11))
1165 #define MODE_AG_BW_20MHZ_8723B (BIT(10) | BIT(11))
1166 #define MODE_AG_BW_40MHZ_8723B BIT(10)