Lines Matching refs:reg
48 u32 reg; in rt2500pci_bbp_write() local
56 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2500pci_bbp_write()
57 reg = 0; in rt2500pci_bbp_write()
58 rt2x00_set_field32(®, BBPCSR_VALUE, value); in rt2500pci_bbp_write()
59 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2500pci_bbp_write()
60 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2500pci_bbp_write()
61 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); in rt2500pci_bbp_write()
63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2500pci_bbp_write()
72 u32 reg; in rt2500pci_bbp_read() local
85 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2500pci_bbp_read()
86 reg = 0; in rt2500pci_bbp_read()
87 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2500pci_bbp_read()
88 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2500pci_bbp_read()
89 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); in rt2500pci_bbp_read()
91 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2500pci_bbp_read()
93 WAIT_FOR_BBP(rt2x00dev, ®); in rt2500pci_bbp_read()
96 value = rt2x00_get_field32(reg, BBPCSR_VALUE); in rt2500pci_bbp_read()
106 u32 reg; in rt2500pci_rf_write() local
114 if (WAIT_FOR_RF(rt2x00dev, ®)) { in rt2500pci_rf_write()
115 reg = 0; in rt2500pci_rf_write()
116 rt2x00_set_field32(®, RFCSR_VALUE, value); in rt2500pci_rf_write()
117 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); in rt2500pci_rf_write()
118 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); in rt2500pci_rf_write()
119 rt2x00_set_field32(®, RFCSR_BUSY, 1); in rt2500pci_rf_write()
121 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg); in rt2500pci_rf_write()
131 u32 reg; in rt2500pci_eepromregister_read() local
133 reg = rt2x00mmio_register_read(rt2x00dev, CSR21); in rt2500pci_eepromregister_read()
135 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); in rt2500pci_eepromregister_read()
136 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); in rt2500pci_eepromregister_read()
138 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK); in rt2500pci_eepromregister_read()
140 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT); in rt2500pci_eepromregister_read()
146 u32 reg = 0; in rt2500pci_eepromregister_write() local
148 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); in rt2500pci_eepromregister_write()
149 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); in rt2500pci_eepromregister_write()
150 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, in rt2500pci_eepromregister_write()
152 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, in rt2500pci_eepromregister_write()
155 rt2x00mmio_register_write(rt2x00dev, CSR21, reg); in rt2500pci_eepromregister_write()
195 u32 reg; in rt2500pci_rfkill_poll() local
197 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR); in rt2500pci_rfkill_poll()
198 return rt2x00_get_field32(reg, GPIOCSR_VAL0); in rt2500pci_rfkill_poll()
208 u32 reg; in rt2500pci_brightness_set() local
210 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR); in rt2500pci_brightness_set()
213 rt2x00_set_field32(®, LEDCSR_LINK, enabled); in rt2500pci_brightness_set()
215 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled); in rt2500pci_brightness_set()
217 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2500pci_brightness_set()
226 u32 reg; in rt2500pci_blink_set() local
228 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR); in rt2500pci_blink_set()
229 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on); in rt2500pci_blink_set()
230 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off); in rt2500pci_blink_set()
231 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2500pci_blink_set()
254 u32 reg; in rt2500pci_config_filter() local
262 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); in rt2500pci_config_filter()
263 rt2x00_set_field32(®, RXCSR0_DROP_CRC, in rt2500pci_config_filter()
265 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, in rt2500pci_config_filter()
267 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, in rt2500pci_config_filter()
269 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, in rt2500pci_config_filter()
271 rt2x00_set_field32(®, RXCSR0_DROP_TODS, in rt2500pci_config_filter()
274 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); in rt2500pci_config_filter()
275 rt2x00_set_field32(®, RXCSR0_DROP_MCAST, in rt2500pci_config_filter()
277 rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0); in rt2500pci_config_filter()
278 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2500pci_config_filter()
288 u32 reg; in rt2500pci_config_intf() local
295 reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1); in rt2500pci_config_intf()
296 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload); in rt2500pci_config_intf()
297 rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN, queue->cw_min); in rt2500pci_config_intf()
298 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg); in rt2500pci_config_intf()
303 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2500pci_config_intf()
304 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); in rt2500pci_config_intf()
305 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_config_intf()
322 u32 reg; in rt2500pci_config_erp() local
330 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1); in rt2500pci_config_erp()
331 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x162); in rt2500pci_config_erp()
332 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0xa2); in rt2500pci_config_erp()
333 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); in rt2500pci_config_erp()
334 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); in rt2500pci_config_erp()
335 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg); in rt2500pci_config_erp()
337 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2); in rt2500pci_config_erp()
338 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); in rt2500pci_config_erp()
339 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); in rt2500pci_config_erp()
340 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2500pci_config_erp()
342 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg); in rt2500pci_config_erp()
344 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3); in rt2500pci_config_erp()
345 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); in rt2500pci_config_erp()
346 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); in rt2500pci_config_erp()
347 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2500pci_config_erp()
349 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg); in rt2500pci_config_erp()
351 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4); in rt2500pci_config_erp()
352 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); in rt2500pci_config_erp()
353 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); in rt2500pci_config_erp()
354 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2500pci_config_erp()
356 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg); in rt2500pci_config_erp()
358 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5); in rt2500pci_config_erp()
359 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); in rt2500pci_config_erp()
360 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); in rt2500pci_config_erp()
361 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2500pci_config_erp()
363 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg); in rt2500pci_config_erp()
370 reg = rt2x00mmio_register_read(rt2x00dev, CSR11); in rt2500pci_config_erp()
371 rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); in rt2500pci_config_erp()
372 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2500pci_config_erp()
374 reg = rt2x00mmio_register_read(rt2x00dev, CSR18); in rt2500pci_config_erp()
375 rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); in rt2500pci_config_erp()
376 rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); in rt2500pci_config_erp()
377 rt2x00mmio_register_write(rt2x00dev, CSR18, reg); in rt2500pci_config_erp()
379 reg = rt2x00mmio_register_read(rt2x00dev, CSR19); in rt2500pci_config_erp()
380 rt2x00_set_field32(®, CSR19_DIFS, erp->difs); in rt2500pci_config_erp()
381 rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); in rt2500pci_config_erp()
382 rt2x00mmio_register_write(rt2x00dev, CSR19, reg); in rt2500pci_config_erp()
386 reg = rt2x00mmio_register_read(rt2x00dev, CSR12); in rt2500pci_config_erp()
387 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, in rt2500pci_config_erp()
389 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, in rt2500pci_config_erp()
391 rt2x00mmio_register_write(rt2x00dev, CSR12, reg); in rt2500pci_config_erp()
399 u32 reg; in rt2500pci_config_ant() local
410 reg = rt2x00mmio_register_read(rt2x00dev, BBPCSR1); in rt2500pci_config_ant()
420 rt2x00_set_field32(®, BBPCSR1_CCK, 0); in rt2500pci_config_ant()
421 rt2x00_set_field32(®, BBPCSR1_OFDM, 0); in rt2500pci_config_ant()
426 rt2x00_set_field32(®, BBPCSR1_CCK, 2); in rt2500pci_config_ant()
427 rt2x00_set_field32(®, BBPCSR1_OFDM, 2); in rt2500pci_config_ant()
449 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 1); in rt2500pci_config_ant()
450 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 1); in rt2500pci_config_ant()
458 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 0); in rt2500pci_config_ant()
459 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 0); in rt2500pci_config_ant()
462 rt2x00mmio_register_write(rt2x00dev, BBPCSR1, reg); in rt2500pci_config_ant()
549 u32 reg; in rt2500pci_config_retry_limit() local
551 reg = rt2x00mmio_register_read(rt2x00dev, CSR11); in rt2500pci_config_retry_limit()
552 rt2x00_set_field32(®, CSR11_LONG_RETRY, in rt2500pci_config_retry_limit()
554 rt2x00_set_field32(®, CSR11_SHORT_RETRY, in rt2500pci_config_retry_limit()
556 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2500pci_config_retry_limit()
565 u32 reg; in rt2500pci_config_ps() local
568 reg = rt2x00mmio_register_read(rt2x00dev, CSR20); in rt2500pci_config_ps()
569 rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN, in rt2500pci_config_ps()
571 rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP, in rt2500pci_config_ps()
575 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); in rt2500pci_config_ps()
576 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2500pci_config_ps()
578 rt2x00_set_field32(®, CSR20_AUTOWAKE, 1); in rt2500pci_config_ps()
579 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2500pci_config_ps()
581 reg = rt2x00mmio_register_read(rt2x00dev, CSR20); in rt2500pci_config_ps()
582 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); in rt2500pci_config_ps()
583 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2500pci_config_ps()
612 u32 reg; in rt2500pci_link_stats() local
617 reg = rt2x00mmio_register_read(rt2x00dev, CNT0); in rt2500pci_link_stats()
618 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); in rt2500pci_link_stats()
623 reg = rt2x00mmio_register_read(rt2x00dev, CNT3); in rt2500pci_link_stats()
624 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA); in rt2500pci_link_stats()
719 u32 reg; in rt2500pci_start_queue() local
723 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); in rt2500pci_start_queue()
724 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0); in rt2500pci_start_queue()
725 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2500pci_start_queue()
728 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2500pci_start_queue()
729 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); in rt2500pci_start_queue()
730 rt2x00_set_field32(®, CSR14_TBCN, 1); in rt2500pci_start_queue()
731 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2500pci_start_queue()
732 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_start_queue()
742 u32 reg; in rt2500pci_kick_queue() local
746 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); in rt2500pci_kick_queue()
747 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1); in rt2500pci_kick_queue()
748 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2500pci_kick_queue()
751 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); in rt2500pci_kick_queue()
752 rt2x00_set_field32(®, TXCSR0_KICK_TX, 1); in rt2500pci_kick_queue()
753 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2500pci_kick_queue()
756 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); in rt2500pci_kick_queue()
757 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1); in rt2500pci_kick_queue()
758 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2500pci_kick_queue()
768 u32 reg; in rt2500pci_stop_queue() local
774 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); in rt2500pci_stop_queue()
775 rt2x00_set_field32(®, TXCSR0_ABORT, 1); in rt2500pci_stop_queue()
776 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2500pci_stop_queue()
779 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); in rt2500pci_stop_queue()
780 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1); in rt2500pci_stop_queue()
781 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2500pci_stop_queue()
784 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2500pci_stop_queue()
785 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); in rt2500pci_stop_queue()
786 rt2x00_set_field32(®, CSR14_TBCN, 0); in rt2500pci_stop_queue()
787 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2500pci_stop_queue()
788 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_stop_queue()
845 u32 reg; in rt2500pci_init_queues() local
850 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2); in rt2500pci_init_queues()
851 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); in rt2500pci_init_queues()
852 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); in rt2500pci_init_queues()
853 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); in rt2500pci_init_queues()
854 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); in rt2500pci_init_queues()
855 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg); in rt2500pci_init_queues()
858 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3); in rt2500pci_init_queues()
859 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, in rt2500pci_init_queues()
861 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg); in rt2500pci_init_queues()
864 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5); in rt2500pci_init_queues()
865 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, in rt2500pci_init_queues()
867 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg); in rt2500pci_init_queues()
870 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4); in rt2500pci_init_queues()
871 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, in rt2500pci_init_queues()
873 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg); in rt2500pci_init_queues()
876 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6); in rt2500pci_init_queues()
877 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, in rt2500pci_init_queues()
879 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg); in rt2500pci_init_queues()
881 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1); in rt2500pci_init_queues()
882 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); in rt2500pci_init_queues()
883 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); in rt2500pci_init_queues()
884 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg); in rt2500pci_init_queues()
887 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2); in rt2500pci_init_queues()
888 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, in rt2500pci_init_queues()
890 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg); in rt2500pci_init_queues()
897 u32 reg; in rt2500pci_init_registers() local
904 reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR); in rt2500pci_init_registers()
905 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33); in rt2500pci_init_registers()
906 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63); in rt2500pci_init_registers()
907 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); in rt2500pci_init_registers()
908 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg); in rt2500pci_init_registers()
910 reg = rt2x00mmio_register_read(rt2x00dev, CSR9); in rt2500pci_init_registers()
911 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, in rt2500pci_init_registers()
913 rt2x00mmio_register_write(rt2x00dev, CSR9, reg); in rt2500pci_init_registers()
918 reg = rt2x00mmio_register_read(rt2x00dev, CSR11); in rt2500pci_init_registers()
919 rt2x00_set_field32(®, CSR11_CW_SELECT, 0); in rt2500pci_init_registers()
920 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2500pci_init_registers()
922 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2500pci_init_registers()
923 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); in rt2500pci_init_registers()
924 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); in rt2500pci_init_registers()
925 rt2x00_set_field32(®, CSR14_TBCN, 0); in rt2500pci_init_registers()
926 rt2x00_set_field32(®, CSR14_TCFP, 0); in rt2500pci_init_registers()
927 rt2x00_set_field32(®, CSR14_TATIMW, 0); in rt2500pci_init_registers()
928 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2500pci_init_registers()
929 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); in rt2500pci_init_registers()
930 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); in rt2500pci_init_registers()
931 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_init_registers()
935 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR8); in rt2500pci_init_registers()
936 rt2x00_set_field32(®, TXCSR8_BBP_ID0, 10); in rt2500pci_init_registers()
937 rt2x00_set_field32(®, TXCSR8_BBP_ID0_VALID, 1); in rt2500pci_init_registers()
938 rt2x00_set_field32(®, TXCSR8_BBP_ID1, 11); in rt2500pci_init_registers()
939 rt2x00_set_field32(®, TXCSR8_BBP_ID1_VALID, 1); in rt2500pci_init_registers()
940 rt2x00_set_field32(®, TXCSR8_BBP_ID2, 13); in rt2500pci_init_registers()
941 rt2x00_set_field32(®, TXCSR8_BBP_ID2_VALID, 1); in rt2500pci_init_registers()
942 rt2x00_set_field32(®, TXCSR8_BBP_ID3, 12); in rt2500pci_init_registers()
943 rt2x00_set_field32(®, TXCSR8_BBP_ID3_VALID, 1); in rt2500pci_init_registers()
944 rt2x00mmio_register_write(rt2x00dev, TXCSR8, reg); in rt2500pci_init_registers()
946 reg = rt2x00mmio_register_read(rt2x00dev, ARTCSR0); in rt2500pci_init_registers()
947 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_1MBS, 112); in rt2500pci_init_registers()
948 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_2MBS, 56); in rt2500pci_init_registers()
949 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_5_5MBS, 20); in rt2500pci_init_registers()
950 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_11MBS, 10); in rt2500pci_init_registers()
951 rt2x00mmio_register_write(rt2x00dev, ARTCSR0, reg); in rt2500pci_init_registers()
953 reg = rt2x00mmio_register_read(rt2x00dev, ARTCSR1); in rt2500pci_init_registers()
954 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_6MBS, 45); in rt2500pci_init_registers()
955 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_9MBS, 37); in rt2500pci_init_registers()
956 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_12MBS, 33); in rt2500pci_init_registers()
957 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_18MBS, 29); in rt2500pci_init_registers()
958 rt2x00mmio_register_write(rt2x00dev, ARTCSR1, reg); in rt2500pci_init_registers()
960 reg = rt2x00mmio_register_read(rt2x00dev, ARTCSR2); in rt2500pci_init_registers()
961 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_24MBS, 29); in rt2500pci_init_registers()
962 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_36MBS, 25); in rt2500pci_init_registers()
963 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_48MBS, 25); in rt2500pci_init_registers()
964 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_54MBS, 25); in rt2500pci_init_registers()
965 rt2x00mmio_register_write(rt2x00dev, ARTCSR2, reg); in rt2500pci_init_registers()
967 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3); in rt2500pci_init_registers()
968 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47); /* CCK Signal */ in rt2500pci_init_registers()
969 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); in rt2500pci_init_registers()
970 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51); /* Rssi */ in rt2500pci_init_registers()
971 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); in rt2500pci_init_registers()
972 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 42); /* OFDM Rate */ in rt2500pci_init_registers()
973 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); in rt2500pci_init_registers()
974 rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51); /* RSSI */ in rt2500pci_init_registers()
975 rt2x00_set_field32(®, RXCSR3_BBP_ID3_VALID, 1); in rt2500pci_init_registers()
976 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg); in rt2500pci_init_registers()
978 reg = rt2x00mmio_register_read(rt2x00dev, PCICSR); in rt2500pci_init_registers()
979 rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0); in rt2500pci_init_registers()
980 rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0); in rt2500pci_init_registers()
981 rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3); in rt2500pci_init_registers()
982 rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1); in rt2500pci_init_registers()
983 rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1); in rt2500pci_init_registers()
984 rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1); in rt2500pci_init_registers()
985 rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1); in rt2500pci_init_registers()
986 rt2x00mmio_register_write(rt2x00dev, PCICSR, reg); in rt2500pci_init_registers()
999 reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2); in rt2500pci_init_registers()
1000 rt2x00_set_field32(®, MACCSR2_DELAY, 64); in rt2500pci_init_registers()
1001 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg); in rt2500pci_init_registers()
1003 reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR); in rt2500pci_init_registers()
1004 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); in rt2500pci_init_registers()
1005 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 26); in rt2500pci_init_registers()
1006 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID0, 1); in rt2500pci_init_registers()
1007 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); in rt2500pci_init_registers()
1008 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 26); in rt2500pci_init_registers()
1009 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID1, 1); in rt2500pci_init_registers()
1010 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg); in rt2500pci_init_registers()
1016 reg = rt2x00mmio_register_read(rt2x00dev, CSR1); in rt2500pci_init_registers()
1017 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1); in rt2500pci_init_registers()
1018 rt2x00_set_field32(®, CSR1_BBP_RESET, 0); in rt2500pci_init_registers()
1019 rt2x00_set_field32(®, CSR1_HOST_READY, 0); in rt2500pci_init_registers()
1020 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2500pci_init_registers()
1022 reg = rt2x00mmio_register_read(rt2x00dev, CSR1); in rt2500pci_init_registers()
1023 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); in rt2500pci_init_registers()
1024 rt2x00_set_field32(®, CSR1_HOST_READY, 1); in rt2500pci_init_registers()
1025 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2500pci_init_registers()
1032 reg = rt2x00mmio_register_read(rt2x00dev, CNT0); in rt2500pci_init_registers()
1033 reg = rt2x00mmio_register_read(rt2x00dev, CNT4); in rt2500pci_init_registers()
1115 u32 reg; in rt2500pci_toggle_irq() local
1123 reg = rt2x00mmio_register_read(rt2x00dev, CSR7); in rt2500pci_toggle_irq()
1124 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2500pci_toggle_irq()
1133 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); in rt2500pci_toggle_irq()
1134 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); in rt2500pci_toggle_irq()
1135 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); in rt2500pci_toggle_irq()
1136 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); in rt2500pci_toggle_irq()
1137 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); in rt2500pci_toggle_irq()
1138 rt2x00_set_field32(®, CSR8_RXDONE, mask); in rt2500pci_toggle_irq()
1139 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2500pci_toggle_irq()
1177 u32 reg, reg2; in rt2500pci_set_state() local
1185 reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1); in rt2500pci_set_state()
1186 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); in rt2500pci_set_state()
1187 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); in rt2500pci_set_state()
1188 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); in rt2500pci_set_state()
1189 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); in rt2500pci_set_state()
1190 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2500pci_set_state()
1203 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2500pci_set_state()
1321 u32 reg; in rt2500pci_write_beacon() local
1327 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2500pci_write_beacon()
1328 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2500pci_write_beacon()
1329 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_write_beacon()
1349 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2500pci_write_beacon()
1350 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2500pci_write_beacon()
1435 u32 reg; in rt2500pci_enable_interrupt() local
1443 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); in rt2500pci_enable_interrupt()
1444 rt2x00_set_field32(®, irq_field, 0); in rt2500pci_enable_interrupt()
1445 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2500pci_enable_interrupt()
1454 u32 reg; in rt2500pci_txstatus_tasklet() local
1469 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); in rt2500pci_txstatus_tasklet()
1470 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); in rt2500pci_txstatus_tasklet()
1471 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0); in rt2500pci_txstatus_tasklet()
1472 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); in rt2500pci_txstatus_tasklet()
1473 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2500pci_txstatus_tasklet()
1500 u32 reg, mask; in rt2500pci_interrupt() local
1506 reg = rt2x00mmio_register_read(rt2x00dev, CSR7); in rt2500pci_interrupt()
1507 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2500pci_interrupt()
1509 if (!reg) in rt2500pci_interrupt()
1515 mask = reg; in rt2500pci_interrupt()
1520 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) in rt2500pci_interrupt()
1523 if (rt2x00_get_field32(reg, CSR7_RXDONE)) in rt2500pci_interrupt()
1526 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) || in rt2500pci_interrupt()
1527 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) || in rt2500pci_interrupt()
1528 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) { in rt2500pci_interrupt()
1544 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); in rt2500pci_interrupt()
1545 reg |= mask; in rt2500pci_interrupt()
1546 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2500pci_interrupt()
1559 u32 reg; in rt2500pci_validate_eeprom() local
1563 reg = rt2x00mmio_register_read(rt2x00dev, CSR21); in rt2500pci_validate_eeprom()
1568 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? in rt2500pci_validate_eeprom()
1623 u32 reg; in rt2500pci_init_eeprom() local
1636 reg = rt2x00mmio_register_read(rt2x00dev, CSR0); in rt2500pci_init_eeprom()
1638 rt2x00_get_field32(reg, CSR0_REVISION)); in rt2500pci_init_eeprom()
1935 u32 reg; in rt2500pci_probe_hw() local
1952 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR); in rt2500pci_probe_hw()
1953 rt2x00_set_field32(®, GPIOCSR_DIR0, 1); in rt2500pci_probe_hw()
1954 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg); in rt2500pci_probe_hw()
1986 u32 reg; in rt2500pci_get_tsf() local
1988 reg = rt2x00mmio_register_read(rt2x00dev, CSR17); in rt2500pci_get_tsf()
1989 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; in rt2500pci_get_tsf()
1990 reg = rt2x00mmio_register_read(rt2x00dev, CSR16); in rt2500pci_get_tsf()
1991 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); in rt2500pci_get_tsf()
1999 u32 reg; in rt2500pci_tx_last_beacon() local
2001 reg = rt2x00mmio_register_read(rt2x00dev, CSR15); in rt2500pci_tx_last_beacon()
2002 return rt2x00_get_field32(reg, CSR15_BEACON_SENT); in rt2500pci_tx_last_beacon()