Lines Matching +full:12 +full:- +full:bit
1 /* SPDX-License-Identifier: ISC */
14 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
15 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
30 #define MT_RXD1_NORMAL_GROUP_1 BIT(11)
31 #define MT_RXD1_NORMAL_GROUP_2 BIT(12)
32 #define MT_RXD1_NORMAL_GROUP_3 BIT(13)
33 #define MT_RXD1_NORMAL_GROUP_4 BIT(14)
34 #define MT_RXD1_NORMAL_GROUP_5 BIT(15)
37 #define MT_RXD1_NORMAL_CM BIT(23)
38 #define MT_RXD1_NORMAL_CLM BIT(24)
39 #define MT_RXD1_NORMAL_ICV_ERR BIT(25)
40 #define MT_RXD1_NORMAL_TKIP_MIC_ERR BIT(26)
41 #define MT_RXD1_NORMAL_FCS_ERR BIT(27)
42 #define MT_RXD1_NORMAL_BAND_IDX BIT(28)
43 #define MT_RXD1_NORMAL_SPP_EN BIT(29)
44 #define MT_RXD1_NORMAL_ADD_OM BIT(30)
45 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
49 #define MT_RXD2_NORMAL_CO_ANT BIT(6)
50 #define MT_RXD2_NORMAL_BF_CQI BIT(7)
51 #define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)
52 #define MT_RXD2_NORMAL_HDR_TRANS BIT(13)
55 #define MT_RXD2_NORMAL_MU_BAR BIT(21)
56 #define MT_RXD2_NORMAL_SW_BIT BIT(22)
57 #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
58 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
59 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)
60 #define MT_RXD2_NORMAL_INT_FRAME BIT(26)
61 #define MT_RXD2_NORMAL_FRAG BIT(27)
62 #define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
63 #define MT_RXD2_NORMAL_NDATA BIT(29)
64 #define MT_RXD2_NORMAL_NON_AMPDU BIT(30)
65 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
71 #define MT_RXD3_NORMAL_U2M BIT(0)
72 #define MT_RXD3_NORMAL_HTC_VLD BIT(0)
73 #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(19)
74 #define MT_RXD3_NORMAL_BEACON_MC BIT(20)
75 #define MT_RXD3_NORMAL_BEACON_UC BIT(21)
76 #define MT_RXD3_NORMAL_AMSDU BIT(22)
77 #define MT_RXD3_NORMAL_MESH BIT(23)
78 #define MT_RXD3_NORMAL_MHCP BIT(24)
79 #define MT_RXD3_NORMAL_NO_INFO_WB BIT(25)
80 #define MT_RXD3_NORMAL_DISABLE_RX_HDR_TRANS BIT(26)
81 #define MT_RXD3_NORMAL_POWER_SAVE_STAT BIT(27)
82 #define MT_RXD3_NORMAL_MORE BIT(28)
83 #define MT_RXD3_NORMAL_UNWANT BIT(29)
84 #define MT_RXD3_NORMAL_RX_DROP BIT(30)
85 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
89 #define MT_RXD4_NORMAL_PATTERN_DROP BIT(9)
90 #define MT_RXD4_NORMAL_CLS BIT(10)
91 #define MT_RXD4_NORMAL_OFLD GENMASK(12, 11)
92 #define MT_RXD4_NORMAL_MAGIC_PKT BIT(13)
95 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
98 /* P-RXV */
100 #define MT_PRXV_TX_DCM BIT(4)
101 #define MT_PRXV_TX_ER_SU_106T BIT(5)
103 #define MT_PRXV_HT_AD_CODE BIT(11)
111 /* C-RXV */
117 #define MT_CRXV_HE_LDPC_EXT_SYM BIT(20)
118 #define MT_CRXV_HE_PE_DISAMBIG BIT(23)
119 #define MT_CRXV_HE_UPLINK BIT(31)
122 #define MT_CRXV_HE_SR1_MASK GENMASK(16, 12)
127 #define MT_CRXV_HE_TXOP_DUR GENMASK(12, 6)
128 #define MT_CRXV_HE_BEAM_CHNG BIT(13)
129 #define MT_CRXV_HE_DOPPLER BIT(16)
158 #define MT_CT_INFO_APPLY_TXD BIT(0)
159 #define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
160 #define MT_CT_INFO_MGMT_FRAME BIT(2)
161 #define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
162 #define MT_CT_INFO_HSR2_TX BIT(4)
171 #define MT_TXD1_LONG_FORMAT BIT(31)
172 #define MT_TXD1_TGID BIT(30)
174 #define MT_TXD1_AMSDU BIT(23)
179 #define MT_TXD1_VTA BIT(10)
182 #define MT_TXD2_FIX_RATE BIT(31)
183 #define MT_TXD2_FIXED_RATE BIT(30)
187 #define MT_TXD2_HTC_VLD BIT(13)
188 #define MT_TXD2_DURATION BIT(12)
189 #define MT_TXD2_BIP BIT(11)
190 #define MT_TXD2_MULTICAST BIT(10)
191 #define MT_TXD2_RTS BIT(9)
192 #define MT_TXD2_SOUNDING BIT(8)
193 #define MT_TXD2_NDPA BIT(7)
194 #define MT_TXD2_NDP BIT(6)
198 #define MT_TXD3_SN_VALID BIT(31)
199 #define MT_TXD3_PN_VALID BIT(30)
200 #define MT_TXD3_SW_POWER_MGMT BIT(29)
201 #define MT_TXD3_BA_DISABLE BIT(28)
205 #define MT_TXD3_TIMING_MEASURE BIT(5)
206 #define MT_TXD3_DAS BIT(4)
207 #define MT_TXD3_EEOSP BIT(3)
208 #define MT_TXD3_EMRD BIT(2)
209 #define MT_TXD3_PROTECT_FRAME BIT(1)
210 #define MT_TXD3_NO_ACK BIT(0)
215 #define MT_TXD5_MD BIT(15)
216 #define MT_TXD5_ADD_BA BIT(14)
217 #define MT_TXD5_TX_STATUS_HOST BIT(10)
218 #define MT_TXD5_TX_STATUS_MCU BIT(9)
219 #define MT_TXD5_TX_STATUS_FMT BIT(8)
222 #define MT_TXD6_TX_IBF BIT(31)
223 #define MT_TXD6_TX_EBF BIT(30)
226 #define MT_TXD6_HELTF GENMASK(13, 12)
227 #define MT_TXD6_LDPC BIT(11)
228 #define MT_TXD6_SPE_ID_IDX BIT(10)
230 #define MT_TXD6_DYN_BW BIT(3)
231 #define MT_TXD6_FIXED_BW BIT(2)
235 #define MT_TXD7_UDP_TCP_SUM BIT(29)
236 #define MT_TXD7_IP_SUM BIT(28)
243 #define MT_TXD7_HW_AMSDU BIT(10)
246 #define MT_TX_RATE_STBC BIT(13)
247 #define MT_TX_RATE_NSS GENMASK(12, 10)
274 #define MT_TX_FREE_LATENCY GENMASK(12, 0)
278 #define MT_TX_FREE_PAIR BIT(31)