Lines Matching full:trans
74 #include "iwl-trans.h"
90 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) in iwl_trans_pcie_dump_regs() argument
96 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_dump_regs()
120 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); in iwl_trans_pcie_dump_regs()
124 IWL_ERR(trans, "iwlwifi device config registers:\n"); in iwl_trans_pcie_dump_regs()
130 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); in iwl_trans_pcie_dump_regs()
132 *ptr = iwl_read32(trans, i); in iwl_trans_pcie_dump_regs()
137 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); in iwl_trans_pcie_dump_regs()
152 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", in iwl_trans_pcie_dump_regs()
165 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", in iwl_trans_pcie_dump_regs()
178 IWL_ERR(trans, "Read failed at 0x%X\n", i); in iwl_trans_pcie_dump_regs()
184 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) in iwl_trans_pcie_sw_reset() argument
187 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); in iwl_trans_pcie_sw_reset()
191 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) in iwl_pcie_free_fw_monitor() argument
193 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_free_fw_monitor()
198 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, in iwl_pcie_free_fw_monitor()
206 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, in iwl_pcie_alloc_fw_monitor_block() argument
209 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_alloc_fw_monitor_block()
220 block = dma_alloc_coherent(trans->dev, size, &physical, in iwl_pcie_alloc_fw_monitor_block()
225 IWL_INFO(trans, in iwl_pcie_alloc_fw_monitor_block()
235 IWL_ERR(trans, in iwl_pcie_alloc_fw_monitor_block()
245 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) in iwl_pcie_alloc_fw_monitor() argument
259 if (trans->dbg.fw_mon.size) in iwl_pcie_alloc_fw_monitor()
262 iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); in iwl_pcie_alloc_fw_monitor()
265 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) in iwl_trans_pcie_read_shr() argument
267 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, in iwl_trans_pcie_read_shr()
269 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); in iwl_trans_pcie_read_shr()
272 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) in iwl_trans_pcie_write_shr() argument
274 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); in iwl_trans_pcie_write_shr()
275 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, in iwl_trans_pcie_write_shr()
279 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) in iwl_pcie_set_pwr() argument
281 if (trans->cfg->apmg_not_supported) in iwl_pcie_set_pwr()
284 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) in iwl_pcie_set_pwr()
285 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, in iwl_pcie_set_pwr()
289 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, in iwl_pcie_set_pwr()
297 void iwl_pcie_apm_config(struct iwl_trans *trans) in iwl_pcie_apm_config() argument
299 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_apm_config()
308 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); in iwl_pcie_apm_config()
311 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); in iwl_pcie_apm_config()
314 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; in iwl_pcie_apm_config()
315 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", in iwl_pcie_apm_config()
317 trans->ltr_enabled ? "En" : "Dis"); in iwl_pcie_apm_config()
325 static int iwl_pcie_apm_init(struct iwl_trans *trans) in iwl_pcie_apm_init() argument
329 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); in iwl_pcie_apm_init()
337 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) in iwl_pcie_apm_init()
338 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, in iwl_pcie_apm_init()
345 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, in iwl_pcie_apm_init()
349 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); in iwl_pcie_apm_init()
355 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_init()
358 iwl_pcie_apm_config(trans); in iwl_pcie_apm_init()
361 if (trans->trans_cfg->base_params->pll_cfg) in iwl_pcie_apm_init()
362 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); in iwl_pcie_apm_init()
364 ret = iwl_finish_nic_init(trans, trans->trans_cfg); in iwl_pcie_apm_init()
368 if (trans->cfg->host_interrupt_operation_mode) { in iwl_pcie_apm_init()
383 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
384 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
385 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); in iwl_pcie_apm_init()
386 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
387 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
397 if (!trans->cfg->apmg_not_supported) { in iwl_pcie_apm_init()
398 iwl_write_prph(trans, APMG_CLK_EN_REG, in iwl_pcie_apm_init()
403 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, in iwl_pcie_apm_init()
407 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, in iwl_pcie_apm_init()
411 set_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_init()
423 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) in iwl_pcie_apm_lp_xtal_enable() argument
431 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
434 iwl_trans_pcie_sw_reset(trans); in iwl_pcie_apm_lp_xtal_enable()
436 ret = iwl_finish_nic_init(trans, trans->trans_cfg); in iwl_pcie_apm_lp_xtal_enable()
439 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
448 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, in iwl_pcie_apm_lp_xtal_enable()
455 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, in iwl_pcie_apm_lp_xtal_enable()
457 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, in iwl_pcie_apm_lp_xtal_enable()
461 iwl_trans_pcie_sw_reset(trans); in iwl_pcie_apm_lp_xtal_enable()
464 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); in iwl_pcie_apm_lp_xtal_enable()
465 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | in iwl_pcie_apm_lp_xtal_enable()
470 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); in iwl_pcie_apm_lp_xtal_enable()
471 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & in iwl_pcie_apm_lp_xtal_enable()
478 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_lp_xtal_enable()
485 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_pcie_apm_lp_xtal_enable()
488 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, in iwl_pcie_apm_lp_xtal_enable()
492 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
497 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, in iwl_pcie_apm_lp_xtal_enable()
502 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) in iwl_pcie_apm_stop_master() argument
507 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); in iwl_pcie_apm_stop_master()
509 ret = iwl_poll_bit(trans, CSR_RESET, in iwl_pcie_apm_stop_master()
513 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); in iwl_pcie_apm_stop_master()
515 IWL_DEBUG_INFO(trans, "stop master\n"); in iwl_pcie_apm_stop_master()
518 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) in iwl_pcie_apm_stop() argument
520 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); in iwl_pcie_apm_stop()
523 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_apm_stop()
524 iwl_pcie_apm_init(trans); in iwl_pcie_apm_stop()
527 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) in iwl_pcie_apm_stop()
528 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, in iwl_pcie_apm_stop()
530 else if (trans->trans_cfg->device_family >= in iwl_pcie_apm_stop()
532 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_apm_stop()
534 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_stop()
538 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_apm_stop()
544 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_stop()
547 iwl_pcie_apm_stop_master(trans); in iwl_pcie_apm_stop()
549 if (trans->cfg->lp_xtal_workaround) { in iwl_pcie_apm_stop()
550 iwl_pcie_apm_lp_xtal_enable(trans); in iwl_pcie_apm_stop()
554 iwl_trans_pcie_sw_reset(trans); in iwl_pcie_apm_stop()
560 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_pcie_apm_stop()
563 static int iwl_pcie_nic_init(struct iwl_trans *trans) in iwl_pcie_nic_init() argument
565 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_nic_init()
570 ret = iwl_pcie_apm_init(trans); in iwl_pcie_nic_init()
576 iwl_pcie_set_pwr(trans, false); in iwl_pcie_nic_init()
578 iwl_op_mode_nic_config(trans->op_mode); in iwl_pcie_nic_init()
581 iwl_pcie_rx_init(trans); in iwl_pcie_nic_init()
584 if (iwl_pcie_tx_init(trans)) in iwl_pcie_nic_init()
587 if (trans->trans_cfg->base_params->shadow_reg_enable) { in iwl_pcie_nic_init()
589 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); in iwl_pcie_nic_init()
590 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); in iwl_pcie_nic_init()
599 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) in iwl_pcie_set_hw_ready() argument
603 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_set_hw_ready()
607 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_set_hw_ready()
613 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); in iwl_pcie_set_hw_ready()
615 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); in iwl_pcie_set_hw_ready()
620 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) in iwl_pcie_prepare_card_hw() argument
626 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); in iwl_pcie_prepare_card_hw()
628 ret = iwl_pcie_set_hw_ready(trans); in iwl_pcie_prepare_card_hw()
633 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_prepare_card_hw()
639 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_prepare_card_hw()
643 ret = iwl_pcie_set_hw_ready(trans); in iwl_pcie_prepare_card_hw()
653 IWL_ERR(trans, "Couldn't prepare the card\n"); in iwl_pcie_prepare_card_hw()
661 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, in iwl_pcie_load_firmware_chunk_fh() argument
665 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
668 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
671 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
674 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
678 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
683 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
689 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, in iwl_pcie_load_firmware_chunk() argument
693 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_load_firmware_chunk()
699 if (!iwl_trans_grab_nic_access(trans, &flags)) in iwl_pcie_load_firmware_chunk()
702 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, in iwl_pcie_load_firmware_chunk()
704 iwl_trans_release_nic_access(trans, &flags); in iwl_pcie_load_firmware_chunk()
709 IWL_ERR(trans, "Failed to load firmware chunk!\n"); in iwl_pcie_load_firmware_chunk()
710 iwl_trans_pcie_dump_regs(trans); in iwl_pcie_load_firmware_chunk()
717 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, in iwl_pcie_load_section() argument
725 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", in iwl_pcie_load_section()
728 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, in iwl_pcie_load_section()
731 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); in iwl_pcie_load_section()
733 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, in iwl_pcie_load_section()
751 iwl_set_bits_prph(trans, LMPM_CHICK, in iwl_pcie_load_section()
755 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, in iwl_pcie_load_section()
759 iwl_clear_bits_prph(trans, LMPM_CHICK, in iwl_pcie_load_section()
763 IWL_ERR(trans, in iwl_pcie_load_section()
770 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); in iwl_pcie_load_section()
774 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, in iwl_pcie_load_cpu_sections_8000() argument
803 IWL_DEBUG_FW(trans, in iwl_pcie_load_cpu_sections_8000()
809 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections_8000()
814 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); in iwl_pcie_load_cpu_sections_8000()
816 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); in iwl_pcie_load_cpu_sections_8000()
823 iwl_enable_interrupts(trans); in iwl_pcie_load_cpu_sections_8000()
825 if (trans->trans_cfg->use_tfh) { in iwl_pcie_load_cpu_sections_8000()
827 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, in iwl_pcie_load_cpu_sections_8000()
830 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, in iwl_pcie_load_cpu_sections_8000()
834 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, in iwl_pcie_load_cpu_sections_8000()
837 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, in iwl_pcie_load_cpu_sections_8000()
844 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, in iwl_pcie_load_cpu_sections() argument
869 IWL_DEBUG_FW(trans, in iwl_pcie_load_cpu_sections()
875 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections()
885 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) in iwl_pcie_apply_destination_ini() argument
889 &trans->dbg.fw_mon_cfg[alloc_id]; in iwl_pcie_apply_destination_ini()
892 if (!iwl_trans_dbg_ini_valid(trans)) in iwl_pcie_apply_destination_ini()
897 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); in iwl_pcie_apply_destination_ini()
899 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apply_destination_ini()
907 !trans->dbg.fw_mon_ini[alloc_id].num_frags) in iwl_pcie_apply_destination_ini()
910 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; in iwl_pcie_apply_destination_ini()
912 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", in iwl_pcie_apply_destination_ini()
915 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, in iwl_pcie_apply_destination_ini()
917 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, in iwl_pcie_apply_destination_ini()
922 void iwl_pcie_apply_destination(struct iwl_trans *trans) in iwl_pcie_apply_destination() argument
924 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; in iwl_pcie_apply_destination()
925 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_apply_destination()
928 if (iwl_trans_dbg_ini_valid(trans)) { in iwl_pcie_apply_destination()
929 iwl_pcie_apply_destination_ini(trans); in iwl_pcie_apply_destination()
933 IWL_INFO(trans, "Applying debug destination %s\n", in iwl_pcie_apply_destination()
937 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); in iwl_pcie_apply_destination()
939 IWL_WARN(trans, "PCI should have external buffer debug\n"); in iwl_pcie_apply_destination()
941 for (i = 0; i < trans->dbg.n_dest_reg; i++) { in iwl_pcie_apply_destination()
947 iwl_write32(trans, addr, val); in iwl_pcie_apply_destination()
950 iwl_set_bit(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
953 iwl_clear_bit(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
956 iwl_write_prph(trans, addr, val); in iwl_pcie_apply_destination()
959 iwl_set_bits_prph(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
962 iwl_clear_bits_prph(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
965 if (iwl_read_prph(trans, addr) & BIT(val)) { in iwl_pcie_apply_destination()
966 IWL_ERR(trans, in iwl_pcie_apply_destination()
973 IWL_ERR(trans, "FW debug - unknown OP %d\n", in iwl_pcie_apply_destination()
981 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), in iwl_pcie_apply_destination()
983 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_pcie_apply_destination()
984 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
988 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
994 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, in iwl_pcie_load_given_ucode() argument
1000 IWL_DEBUG_FW(trans, "working with %s CPU\n", in iwl_pcie_load_given_ucode()
1004 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); in iwl_pcie_load_given_ucode()
1010 iwl_write_prph(trans, in iwl_pcie_load_given_ucode()
1015 ret = iwl_pcie_load_cpu_sections(trans, image, 2, in iwl_pcie_load_given_ucode()
1021 if (iwl_pcie_dbg_on(trans)) in iwl_pcie_load_given_ucode()
1022 iwl_pcie_apply_destination(trans); in iwl_pcie_load_given_ucode()
1024 iwl_enable_interrupts(trans); in iwl_pcie_load_given_ucode()
1027 iwl_write32(trans, CSR_RESET, 0); in iwl_pcie_load_given_ucode()
1032 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, in iwl_pcie_load_given_ucode_8000() argument
1038 IWL_DEBUG_FW(trans, "working with %s CPU\n", in iwl_pcie_load_given_ucode_8000()
1041 if (iwl_pcie_dbg_on(trans)) in iwl_pcie_load_given_ucode_8000()
1042 iwl_pcie_apply_destination(trans); in iwl_pcie_load_given_ucode_8000()
1044 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", in iwl_pcie_load_given_ucode_8000()
1045 iwl_read_prph(trans, WFPM_GP2)); in iwl_pcie_load_given_ucode_8000()
1052 iwl_write_prph(trans, WFPM_GP2, 0x01010101); in iwl_pcie_load_given_ucode_8000()
1056 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); in iwl_pcie_load_given_ucode_8000()
1059 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, in iwl_pcie_load_given_ucode_8000()
1065 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, in iwl_pcie_load_given_ucode_8000()
1069 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) in iwl_pcie_check_hw_rf_kill() argument
1071 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_check_hw_rf_kill()
1072 bool hw_rfkill = iwl_is_rfkill_set(trans); in iwl_pcie_check_hw_rf_kill()
1073 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1077 set_bit(STATUS_RFKILL_HW, &trans->status); in iwl_pcie_check_hw_rf_kill()
1078 set_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1080 clear_bit(STATUS_RFKILL_HW, &trans->status); in iwl_pcie_check_hw_rf_kill()
1082 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1085 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1088 iwl_trans_pcie_rf_kill(trans, report); in iwl_pcie_check_hw_rf_kill()
1117 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) in iwl_pcie_map_non_rx_causes() argument
1119 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_map_non_rx_causes()
1130 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); in iwl_pcie_map_non_rx_causes()
1131 iwl_clear_bit(trans, causes[i].mask_reg, in iwl_pcie_map_non_rx_causes()
1136 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) in iwl_pcie_map_rx_causes() argument
1138 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_map_rx_causes()
1150 for (idx = 1; idx < trans->num_rx_queues; idx++) { in iwl_pcie_map_rx_causes()
1151 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), in iwl_pcie_map_rx_causes()
1155 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); in iwl_pcie_map_rx_causes()
1160 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); in iwl_pcie_map_rx_causes()
1163 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); in iwl_pcie_map_rx_causes()
1168 struct iwl_trans *trans = trans_pcie->trans; in iwl_pcie_conf_msix_hw() local
1171 if (trans->trans_cfg->mq_rx_supported && in iwl_pcie_conf_msix_hw()
1172 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_conf_msix_hw()
1173 iwl_write_umac_prph(trans, UREG_CHICK, in iwl_pcie_conf_msix_hw()
1182 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_conf_msix_hw()
1183 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); in iwl_pcie_conf_msix_hw()
1192 iwl_pcie_map_rx_causes(trans); in iwl_pcie_conf_msix_hw()
1194 iwl_pcie_map_non_rx_causes(trans); in iwl_pcie_conf_msix_hw()
1199 struct iwl_trans *trans = trans_pcie->trans; in iwl_pcie_init_msix() local
1206 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); in iwl_pcie_init_msix()
1208 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); in iwl_pcie_init_msix()
1212 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) in _iwl_trans_pcie_stop_device() argument
1214 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in _iwl_trans_pcie_stop_device()
1224 iwl_disable_interrupts(trans); in _iwl_trans_pcie_stop_device()
1227 iwl_pcie_disable_ict(trans); in _iwl_trans_pcie_stop_device()
1236 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { in _iwl_trans_pcie_stop_device()
1237 IWL_DEBUG_INFO(trans, in _iwl_trans_pcie_stop_device()
1239 iwl_pcie_tx_stop(trans); in _iwl_trans_pcie_stop_device()
1240 iwl_pcie_rx_stop(trans); in _iwl_trans_pcie_stop_device()
1243 if (!trans->cfg->apmg_not_supported) { in _iwl_trans_pcie_stop_device()
1244 iwl_write_prph(trans, APMG_CLK_DIS_REG, in _iwl_trans_pcie_stop_device()
1251 iwl_clear_bit(trans, CSR_GP_CNTRL, in _iwl_trans_pcie_stop_device()
1255 iwl_pcie_apm_stop(trans, false); in _iwl_trans_pcie_stop_device()
1257 iwl_trans_pcie_sw_reset(trans); in _iwl_trans_pcie_stop_device()
1275 iwl_disable_interrupts(trans); in _iwl_trans_pcie_stop_device()
1278 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); in _iwl_trans_pcie_stop_device()
1279 clear_bit(STATUS_INT_ENABLED, &trans->status); in _iwl_trans_pcie_stop_device()
1280 clear_bit(STATUS_TPOWER_PMI, &trans->status); in _iwl_trans_pcie_stop_device()
1286 iwl_enable_rfkill_int(trans); in _iwl_trans_pcie_stop_device()
1289 iwl_pcie_prepare_card_hw(trans); in _iwl_trans_pcie_stop_device()
1292 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) in iwl_pcie_synchronize_irqs() argument
1294 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_synchronize_irqs()
1306 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, in iwl_trans_pcie_start_fw() argument
1309 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_start_fw()
1314 if (iwl_pcie_prepare_card_hw(trans)) { in iwl_trans_pcie_start_fw()
1315 IWL_WARN(trans, "Exit HW not ready\n"); in iwl_trans_pcie_start_fw()
1320 iwl_enable_rfkill_int(trans); in iwl_trans_pcie_start_fw()
1322 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); in iwl_trans_pcie_start_fw()
1329 iwl_disable_interrupts(trans); in iwl_trans_pcie_start_fw()
1332 iwl_pcie_synchronize_irqs(trans); in iwl_trans_pcie_start_fw()
1337 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); in iwl_trans_pcie_start_fw()
1345 IWL_WARN(trans, in iwl_trans_pcie_start_fw()
1352 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwl_trans_pcie_start_fw()
1353 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, in iwl_trans_pcie_start_fw()
1357 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); in iwl_trans_pcie_start_fw()
1359 ret = iwl_pcie_nic_init(trans); in iwl_trans_pcie_start_fw()
1361 IWL_ERR(trans, "Unable to init nic\n"); in iwl_trans_pcie_start_fw()
1372 iwl_enable_fw_load_int(trans); in iwl_trans_pcie_start_fw()
1375 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwl_trans_pcie_start_fw()
1376 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwl_trans_pcie_start_fw()
1379 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_start_fw()
1380 ret = iwl_pcie_load_given_ucode_8000(trans, fw); in iwl_trans_pcie_start_fw()
1382 ret = iwl_pcie_load_given_ucode(trans, fw); in iwl_trans_pcie_start_fw()
1385 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); in iwl_trans_pcie_start_fw()
1394 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) in iwl_trans_pcie_fw_alive() argument
1396 iwl_pcie_reset_ict(trans); in iwl_trans_pcie_fw_alive()
1397 iwl_pcie_tx_start(trans, scd_addr); in iwl_trans_pcie_fw_alive()
1400 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, in iwl_trans_pcie_handle_stop_rfkill() argument
1417 hw_rfkill = iwl_is_rfkill_set(trans); in iwl_trans_pcie_handle_stop_rfkill()
1419 set_bit(STATUS_RFKILL_HW, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1420 set_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1422 clear_bit(STATUS_RFKILL_HW, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1423 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1426 iwl_trans_pcie_rf_kill(trans, hw_rfkill); in iwl_trans_pcie_handle_stop_rfkill()
1429 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) in iwl_trans_pcie_stop_device() argument
1431 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_stop_device()
1436 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_stop_device()
1437 _iwl_trans_pcie_stop_device(trans); in iwl_trans_pcie_stop_device()
1438 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); in iwl_trans_pcie_stop_device()
1442 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) in iwl_trans_pcie_rf_kill() argument
1445 IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_rf_kill()
1449 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", in iwl_trans_pcie_rf_kill()
1451 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { in iwl_trans_pcie_rf_kill()
1452 if (trans->trans_cfg->gen2) in iwl_trans_pcie_rf_kill()
1453 _iwl_trans_pcie_gen2_stop_device(trans); in iwl_trans_pcie_rf_kill()
1455 _iwl_trans_pcie_stop_device(trans); in iwl_trans_pcie_rf_kill()
1459 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, in iwl_pcie_d3_complete_suspend() argument
1462 iwl_disable_interrupts(trans); in iwl_pcie_d3_complete_suspend()
1471 iwl_pcie_disable_ict(trans); in iwl_pcie_d3_complete_suspend()
1473 iwl_pcie_synchronize_irqs(trans); in iwl_pcie_d3_complete_suspend()
1475 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_d3_complete_suspend()
1477 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_pcie_d3_complete_suspend()
1485 iwl_trans_pcie_tx_reset(trans); in iwl_pcie_d3_complete_suspend()
1488 iwl_pcie_set_pwr(trans, true); in iwl_pcie_d3_complete_suspend()
1491 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, in iwl_trans_pcie_d3_suspend() argument
1495 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_d3_suspend()
1499 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_trans_pcie_d3_suspend()
1502 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_d3_suspend()
1503 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, in iwl_trans_pcie_d3_suspend()
1514 IWL_ERR(trans, "Timeout entering D3\n"); in iwl_trans_pcie_d3_suspend()
1518 iwl_pcie_d3_complete_suspend(trans, test, reset); in iwl_trans_pcie_d3_suspend()
1523 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, in iwl_trans_pcie_d3_resume() argument
1527 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_d3_resume()
1532 iwl_enable_interrupts(trans); in iwl_trans_pcie_d3_resume()
1537 iwl_set_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_d3_resume()
1540 ret = iwl_finish_nic_init(trans, trans->trans_cfg); in iwl_trans_pcie_d3_resume()
1553 iwl_pcie_reset_ict(trans); in iwl_trans_pcie_d3_resume()
1554 iwl_enable_interrupts(trans); in iwl_trans_pcie_d3_resume()
1556 iwl_pcie_set_pwr(trans, false); in iwl_trans_pcie_d3_resume()
1559 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_d3_resume()
1562 iwl_trans_pcie_tx_reset(trans); in iwl_trans_pcie_d3_resume()
1564 ret = iwl_pcie_rx_init(trans); in iwl_trans_pcie_d3_resume()
1566 IWL_ERR(trans, in iwl_trans_pcie_d3_resume()
1572 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", in iwl_trans_pcie_d3_resume()
1573 iwl_read_umac_prph(trans, WFPM_GP2)); in iwl_trans_pcie_d3_resume()
1575 val = iwl_read32(trans, CSR_RESET); in iwl_trans_pcie_d3_resume()
1583 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_d3_resume()
1585 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, in iwl_trans_pcie_d3_resume()
1596 IWL_ERR(trans, "Timeout exiting D3\n"); in iwl_trans_pcie_d3_resume()
1605 struct iwl_trans *trans, in iwl_pcie_set_interrupt_capa() argument
1608 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_set_interrupt_capa()
1627 IWL_DEBUG_INFO(trans, in iwl_pcie_set_interrupt_capa()
1634 IWL_DEBUG_INFO(trans, in iwl_pcie_set_interrupt_capa()
1646 trans_pcie->trans->num_rx_queues = num_irqs + 1; in iwl_pcie_set_interrupt_capa()
1650 trans_pcie->trans->num_rx_queues = num_irqs; in iwl_pcie_set_interrupt_capa()
1653 trans_pcie->trans->num_rx_queues = num_irqs - 1; in iwl_pcie_set_interrupt_capa()
1655 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); in iwl_pcie_set_interrupt_capa()
1674 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) in iwl_pcie_irq_set_affinity() argument
1677 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_irq_set_affinity()
1680 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; in iwl_pcie_irq_set_affinity()
1692 IWL_ERR(trans_pcie->trans, in iwl_pcie_irq_set_affinity()
1722 IWL_ERR(trans_pcie->trans, in iwl_pcie_init_msix_handler()
1728 iwl_pcie_irq_set_affinity(trans_pcie->trans); in iwl_pcie_init_msix_handler()
1733 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) in iwl_trans_pcie_clear_persistence_bit() argument
1737 switch (trans->trans_cfg->device_family) { in iwl_trans_pcie_clear_persistence_bit()
1748 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); in iwl_trans_pcie_clear_persistence_bit()
1750 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); in iwl_trans_pcie_clear_persistence_bit()
1753 IWL_ERR(trans, in iwl_trans_pcie_clear_persistence_bit()
1757 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, in iwl_trans_pcie_clear_persistence_bit()
1764 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) in iwl_pcie_gen2_force_power_gating() argument
1768 ret = iwl_finish_nic_init(trans, trans->trans_cfg); in iwl_pcie_gen2_force_power_gating()
1772 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, in iwl_pcie_gen2_force_power_gating()
1775 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, in iwl_pcie_gen2_force_power_gating()
1779 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, in iwl_pcie_gen2_force_power_gating()
1782 iwl_trans_pcie_sw_reset(trans); in iwl_pcie_gen2_force_power_gating()
1787 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) in _iwl_trans_pcie_start_hw() argument
1789 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in _iwl_trans_pcie_start_hw()
1794 err = iwl_pcie_prepare_card_hw(trans); in _iwl_trans_pcie_start_hw()
1796 IWL_ERR(trans, "Error while preparing HW: %d\n", err); in _iwl_trans_pcie_start_hw()
1800 err = iwl_trans_pcie_clear_persistence_bit(trans); in _iwl_trans_pcie_start_hw()
1804 iwl_trans_pcie_sw_reset(trans); in _iwl_trans_pcie_start_hw()
1806 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && in _iwl_trans_pcie_start_hw()
1807 trans->trans_cfg->integrated) { in _iwl_trans_pcie_start_hw()
1808 err = iwl_pcie_gen2_force_power_gating(trans); in _iwl_trans_pcie_start_hw()
1813 err = iwl_pcie_apm_init(trans); in _iwl_trans_pcie_start_hw()
1820 iwl_enable_rfkill_int(trans); in _iwl_trans_pcie_start_hw()
1828 iwl_pcie_check_hw_rf_kill(trans); in _iwl_trans_pcie_start_hw()
1833 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) in iwl_trans_pcie_start_hw() argument
1835 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_start_hw()
1839 ret = _iwl_trans_pcie_start_hw(trans); in iwl_trans_pcie_start_hw()
1845 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) in iwl_trans_pcie_op_mode_leave() argument
1847 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_op_mode_leave()
1852 iwl_disable_interrupts(trans); in iwl_trans_pcie_op_mode_leave()
1854 iwl_pcie_apm_stop(trans, true); in iwl_trans_pcie_op_mode_leave()
1856 iwl_disable_interrupts(trans); in iwl_trans_pcie_op_mode_leave()
1858 iwl_pcie_disable_ict(trans); in iwl_trans_pcie_op_mode_leave()
1862 iwl_pcie_synchronize_irqs(trans); in iwl_trans_pcie_op_mode_leave()
1865 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) in iwl_trans_pcie_write8() argument
1867 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write8()
1870 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) in iwl_trans_pcie_write32() argument
1872 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write32()
1875 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) in iwl_trans_pcie_read32() argument
1877 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_read32()
1880 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) in iwl_trans_pcie_prph_msk() argument
1882 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_prph_msk()
1888 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) in iwl_trans_pcie_read_prph() argument
1890 u32 mask = iwl_trans_pcie_prph_msk(trans); in iwl_trans_pcie_read_prph()
1892 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, in iwl_trans_pcie_read_prph()
1894 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); in iwl_trans_pcie_read_prph()
1897 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, in iwl_trans_pcie_write_prph() argument
1900 u32 mask = iwl_trans_pcie_prph_msk(trans); in iwl_trans_pcie_write_prph()
1902 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, in iwl_trans_pcie_write_prph()
1904 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); in iwl_trans_pcie_write_prph()
1907 static void iwl_trans_pcie_configure(struct iwl_trans *trans, in iwl_trans_pcie_configure() argument
1910 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_configure()
1912 trans->txqs.cmd.q_id = trans_cfg->cmd_queue; in iwl_trans_pcie_configure()
1913 trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; in iwl_trans_pcie_configure()
1914 trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; in iwl_trans_pcie_configure()
1915 trans->txqs.page_offs = trans_cfg->cb_data_offs; in iwl_trans_pcie_configure()
1916 trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); in iwl_trans_pcie_configure()
1932 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_configure()
1935 trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; in iwl_trans_pcie_configure()
1939 trans->command_groups = trans_cfg->command_groups; in iwl_trans_pcie_configure()
1940 trans->command_groups_size = trans_cfg->command_groups_size; in iwl_trans_pcie_configure()
1951 void iwl_trans_pcie_free(struct iwl_trans *trans) in iwl_trans_pcie_free() argument
1953 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_free()
1956 iwl_pcie_synchronize_irqs(trans); in iwl_trans_pcie_free()
1958 if (trans->trans_cfg->gen2) in iwl_trans_pcie_free()
1959 iwl_txq_gen2_tx_free(trans); in iwl_trans_pcie_free()
1961 iwl_pcie_tx_free(trans); in iwl_trans_pcie_free()
1962 iwl_pcie_rx_free(trans); in iwl_trans_pcie_free()
1978 iwl_pcie_free_ict(trans); in iwl_trans_pcie_free()
1981 iwl_pcie_free_fw_monitor(trans); in iwl_trans_pcie_free()
1984 dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size, in iwl_trans_pcie_free()
1989 iwl_trans_free(trans); in iwl_trans_pcie_free()
1992 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) in iwl_trans_pcie_set_pmi() argument
1995 set_bit(STATUS_TPOWER_PMI, &trans->status); in iwl_trans_pcie_set_pmi()
1997 clear_bit(STATUS_TPOWER_PMI, &trans->status); in iwl_trans_pcie_set_pmi()
2023 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, in iwl_trans_pcie_grab_nic_access() argument
2027 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_grab_nic_access()
2035 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_grab_nic_access()
2037 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_grab_nic_access()
2060 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_grab_nic_access()
2065 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); in iwl_trans_pcie_grab_nic_access()
2071 iwl_trans_pcie_dump_regs(trans); in iwl_trans_pcie_grab_nic_access()
2076 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in iwl_trans_pcie_grab_nic_access()
2079 IWL_ERR(trans, "Device gone - scheduling removal!\n"); in iwl_trans_pcie_grab_nic_access()
2088 IWL_ERR(trans, in iwl_trans_pcie_grab_nic_access()
2100 * the trans will be freed and reallocated. in iwl_trans_pcie_grab_nic_access()
2102 set_bit(STATUS_TRANS_DEAD, &trans->status); in iwl_trans_pcie_grab_nic_access()
2104 removal->pdev = to_pci_dev(trans->dev); in iwl_trans_pcie_grab_nic_access()
2109 iwl_write32(trans, CSR_RESET, in iwl_trans_pcie_grab_nic_access()
2127 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, in iwl_trans_pcie_release_nic_access() argument
2130 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_release_nic_access()
2143 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_release_nic_access()
2155 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, in iwl_trans_pcie_read_mem() argument
2166 if (iwl_trans_grab_nic_access(trans, &flags)) { in iwl_trans_pcie_read_mem()
2167 iwl_write32(trans, HBUS_TARG_MEM_RADDR, in iwl_trans_pcie_read_mem()
2171 vals[offs] = iwl_read32(trans, in iwl_trans_pcie_read_mem()
2182 iwl_trans_release_nic_access(trans, &flags); in iwl_trans_pcie_read_mem()
2191 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, in iwl_trans_pcie_write_mem() argument
2198 if (iwl_trans_grab_nic_access(trans, &flags)) { in iwl_trans_pcie_write_mem()
2199 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); in iwl_trans_pcie_write_mem()
2201 iwl_write32(trans, HBUS_TARG_MEM_WDAT, in iwl_trans_pcie_write_mem()
2203 iwl_trans_release_nic_access(trans, &flags); in iwl_trans_pcie_write_mem()
2210 static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, in iwl_trans_pcie_read_config32() argument
2213 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, in iwl_trans_pcie_read_config32()
2217 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, in iwl_trans_pcie_freeze_txq_timer() argument
2224 struct iwl_txq *txq = trans->txqs.txq[queue]; in iwl_trans_pcie_freeze_txq_timer()
2234 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", in iwl_trans_pcie_freeze_txq_timer()
2270 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) in iwl_trans_pcie_block_txq_ptrs() argument
2274 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { in iwl_trans_pcie_block_txq_ptrs()
2275 struct iwl_txq *txq = trans->txqs.txq[i]; in iwl_trans_pcie_block_txq_ptrs()
2277 if (i == trans->txqs.cmd.q_id) in iwl_trans_pcie_block_txq_ptrs()
2285 iwl_write32(trans, HBUS_TARG_WRPTR, in iwl_trans_pcie_block_txq_ptrs()
2298 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, in iwl_trans_pcie_rxq_dma_data() argument
2301 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_rxq_dma_data()
2303 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) in iwl_trans_pcie_rxq_dma_data()
2314 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) in iwl_trans_pcie_wait_txq_empty() argument
2322 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in iwl_trans_pcie_wait_txq_empty()
2325 if (!test_bit(txq_idx, trans->txqs.queue_used)) in iwl_trans_pcie_wait_txq_empty()
2328 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); in iwl_trans_pcie_wait_txq_empty()
2329 txq = trans->txqs.txq[txq_idx]; in iwl_trans_pcie_wait_txq_empty()
2347 * trans layer (overflow TX) don't warn. in iwl_trans_pcie_wait_txq_empty()
2364 IWL_ERR(trans, in iwl_trans_pcie_wait_txq_empty()
2366 iwl_txq_log_scd_error(trans, txq); in iwl_trans_pcie_wait_txq_empty()
2370 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); in iwl_trans_pcie_wait_txq_empty()
2375 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) in iwl_trans_pcie_wait_txqs_empty() argument
2382 cnt < trans->trans_cfg->base_params->num_of_queues; in iwl_trans_pcie_wait_txqs_empty()
2385 if (cnt == trans->txqs.cmd.q_id) in iwl_trans_pcie_wait_txqs_empty()
2387 if (!test_bit(cnt, trans->txqs.queue_used)) in iwl_trans_pcie_wait_txqs_empty()
2392 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); in iwl_trans_pcie_wait_txqs_empty()
2400 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, in iwl_trans_pcie_set_bits_mask() argument
2403 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_set_bits_mask()
2407 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); in iwl_trans_pcie_set_bits_mask()
2445 void iwl_pcie_dump_csr(struct iwl_trans *trans) in iwl_pcie_dump_csr() argument
2474 IWL_ERR(trans, "CSR values:\n"); in iwl_pcie_dump_csr()
2475 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " in iwl_pcie_dump_csr()
2478 IWL_ERR(trans, " %25s: 0X%08x\n", in iwl_pcie_dump_csr()
2480 iwl_read32(trans, csr_tbl[i])); in iwl_pcie_dump_csr()
2487 debugfs_create_file(#name, mode, parent, trans, \
2515 struct iwl_trans *trans; member
2527 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) in iwl_dbgfs_tx_queue_seq_start()
2545 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) in iwl_dbgfs_tx_queue_seq_next()
2560 struct iwl_trans *trans = priv->trans; in iwl_dbgfs_tx_queue_seq_show() local
2561 struct iwl_txq *txq = trans->txqs.txq[state->pos]; in iwl_dbgfs_tx_queue_seq_show()
2565 !!test_bit(state->pos, trans->txqs.queue_used), in iwl_dbgfs_tx_queue_seq_show()
2566 !!test_bit(state->pos, trans->txqs.queue_stopped)); in iwl_dbgfs_tx_queue_seq_show()
2576 if (state->pos == trans->txqs.cmd.q_id) in iwl_dbgfs_tx_queue_seq_show()
2600 priv->trans = inode->i_private; in iwl_dbgfs_tx_queue_open()
2608 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rx_queue_read() local
2609 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_rx_queue_read()
2614 bufsz = sizeof(char) * 121 * trans->num_rx_queues; in iwl_dbgfs_rx_queue_read()
2623 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { in iwl_dbgfs_rx_queue_read()
2639 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, in iwl_dbgfs_rx_queue_read()
2659 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_read() local
2660 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_interrupt_read()
2717 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_write() local
2718 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_interrupt_write()
2736 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_csr_write() local
2738 iwl_pcie_dump_csr(trans); in iwl_dbgfs_csr_write()
2747 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_fh_reg_read() local
2751 ret = iwl_dump_fh(trans, &buf); in iwl_dbgfs_fh_reg_read()
2765 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rfkill_read() local
2766 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_rfkill_read()
2772 !(iwl_read32(trans, CSR_GP_CNTRL) & in iwl_dbgfs_rfkill_read()
2782 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rfkill_write() local
2783 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_rfkill_write()
2792 IWL_WARN(trans, "changing debug rfkill %d->%d\n", in iwl_dbgfs_rfkill_write()
2795 iwl_pcie_handle_rfkill_irq(trans); in iwl_dbgfs_rfkill_write()
2803 struct iwl_trans *trans = inode->i_private; in iwl_dbgfs_monitor_data_open() local
2804 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_monitor_data_open()
2806 if (!trans->dbg.dest_tlv || in iwl_dbgfs_monitor_data_open()
2807 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { in iwl_dbgfs_monitor_data_open()
2808 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); in iwl_dbgfs_monitor_data_open()
2852 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_monitor_data_read() local
2853 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_monitor_data_read()
2854 void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; in iwl_dbgfs_monitor_data_read()
2860 if (trans->dbg.dest_tlv) { in iwl_dbgfs_monitor_data_read()
2862 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); in iwl_dbgfs_monitor_data_read()
2863 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); in iwl_dbgfs_monitor_data_read()
2869 if (unlikely(!trans->dbg.rec_on)) in iwl_dbgfs_monitor_data_read()
2880 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); in iwl_dbgfs_monitor_data_read()
2881 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); in iwl_dbgfs_monitor_data_read()
2893 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
2911 IWL_WARN(trans, in iwl_dbgfs_monitor_data_read()
2915 IWL_WARN(trans, in iwl_dbgfs_monitor_data_read()
2951 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) in iwl_trans_pcie_dbgfs_register() argument
2953 struct dentry *dir = trans->dbgfs_dir; in iwl_trans_pcie_dbgfs_register()
2964 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) in iwl_trans_pcie_debugfs_cleanup() argument
2966 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_debugfs_cleanup()
2975 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) in iwl_trans_pcie_get_cmdlen() argument
2980 for (i = 0; i < trans->txqs.tfd.max_tbs; i++) in iwl_trans_pcie_get_cmdlen()
2981 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); in iwl_trans_pcie_get_cmdlen()
2986 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, in iwl_trans_pcie_dump_rbs() argument
2990 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_dump_rbs()
2998 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; in iwl_trans_pcie_dump_rbs()
3006 dma_unmap_page(trans->dev, rxb->page_dma, max_len, in iwl_trans_pcie_dump_rbs()
3017 rxb->page_dma = dma_map_page(trans->dev, rxb->page, in iwl_trans_pcie_dump_rbs()
3030 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, in iwl_trans_pcie_dump_csr() argument
3042 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); in iwl_trans_pcie_dump_csr()
3049 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, in iwl_trans_pcie_fh_regs_dump() argument
3057 if (!iwl_trans_grab_nic_access(trans, &flags)) in iwl_trans_pcie_fh_regs_dump()
3064 if (!trans->trans_cfg->gen2) in iwl_trans_pcie_fh_regs_dump()
3067 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); in iwl_trans_pcie_fh_regs_dump()
3069 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); in iwl_trans_pcie_fh_regs_dump()
3070 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); in iwl_trans_pcie_fh_regs_dump()
3072 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, in iwl_trans_pcie_fh_regs_dump()
3075 iwl_trans_release_nic_access(trans, &flags); in iwl_trans_pcie_fh_regs_dump()
3083 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, in iwl_trans_pci_dump_marbh_monitor() argument
3092 if (!iwl_trans_grab_nic_access(trans, &flags)) in iwl_trans_pci_dump_marbh_monitor()
3095 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); in iwl_trans_pci_dump_marbh_monitor()
3097 buffer[i] = iwl_read_umac_prph_no_grab(trans, in iwl_trans_pci_dump_marbh_monitor()
3099 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); in iwl_trans_pci_dump_marbh_monitor()
3101 iwl_trans_release_nic_access(trans, &flags); in iwl_trans_pci_dump_marbh_monitor()
3107 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, in iwl_trans_pcie_dump_pointers() argument
3112 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_dump_pointers()
3117 } else if (trans->dbg.dest_tlv) { in iwl_trans_pcie_dump_pointers()
3118 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); in iwl_trans_pcie_dump_pointers()
3119 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); in iwl_trans_pcie_dump_pointers()
3120 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_pcie_dump_pointers()
3127 write_ptr_val = iwl_read_prph(trans, write_ptr); in iwl_trans_pcie_dump_pointers()
3129 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); in iwl_trans_pcie_dump_pointers()
3131 cpu_to_le32(iwl_read_prph(trans, base)); in iwl_trans_pcie_dump_pointers()
3132 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_dump_pointers()
3134 cpu_to_le32(iwl_read_prph(trans, base_high)); in iwl_trans_pcie_dump_pointers()
3141 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, in iwl_trans_pcie_dump_monitor() argument
3145 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_trans_pcie_dump_monitor()
3148 if (trans->dbg.dest_tlv || in iwl_trans_pcie_dump_monitor()
3150 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || in iwl_trans_pcie_dump_monitor()
3151 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { in iwl_trans_pcie_dump_monitor()
3157 iwl_trans_pcie_dump_pointers(trans, fw_mon_data); in iwl_trans_pcie_dump_monitor()
3163 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { in iwl_trans_pcie_dump_monitor()
3169 if (trans->dbg.dest_tlv->version) { in iwl_trans_pcie_dump_monitor()
3170 base = (iwl_read_prph(trans, base) & in iwl_trans_pcie_dump_monitor()
3172 trans->dbg.dest_tlv->base_shift; in iwl_trans_pcie_dump_monitor()
3174 base += trans->cfg->smem_offset; in iwl_trans_pcie_dump_monitor()
3176 base = iwl_read_prph(trans, base) << in iwl_trans_pcie_dump_monitor()
3177 trans->dbg.dest_tlv->base_shift; in iwl_trans_pcie_dump_monitor()
3180 iwl_trans_read_mem(trans, base, fw_mon_data->data, in iwl_trans_pcie_dump_monitor()
3182 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { in iwl_trans_pcie_dump_monitor()
3184 iwl_trans_pci_dump_marbh_monitor(trans, in iwl_trans_pcie_dump_monitor()
3199 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) in iwl_trans_get_fw_monitor_len() argument
3201 if (trans->dbg.fw_mon.size) { in iwl_trans_get_fw_monitor_len()
3204 trans->dbg.fw_mon.size; in iwl_trans_get_fw_monitor_len()
3205 return trans->dbg.fw_mon.size; in iwl_trans_get_fw_monitor_len()
3206 } else if (trans->dbg.dest_tlv) { in iwl_trans_get_fw_monitor_len()
3209 if (trans->dbg.dest_tlv->version == 1) { in iwl_trans_get_fw_monitor_len()
3210 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
3211 cfg_reg = iwl_read_prph(trans, cfg_reg); in iwl_trans_get_fw_monitor_len()
3213 trans->dbg.dest_tlv->base_shift; in iwl_trans_get_fw_monitor_len()
3215 base += trans->cfg->smem_offset; in iwl_trans_get_fw_monitor_len()
3219 trans->dbg.dest_tlv->end_shift; in iwl_trans_get_fw_monitor_len()
3222 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
3223 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); in iwl_trans_get_fw_monitor_len()
3225 base = iwl_read_prph(trans, base) << in iwl_trans_get_fw_monitor_len()
3226 trans->dbg.dest_tlv->base_shift; in iwl_trans_get_fw_monitor_len()
3227 end = iwl_read_prph(trans, end) << in iwl_trans_get_fw_monitor_len()
3228 trans->dbg.dest_tlv->end_shift; in iwl_trans_get_fw_monitor_len()
3231 if (trans->trans_cfg->device_family >= in iwl_trans_get_fw_monitor_len()
3233 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) in iwl_trans_get_fw_monitor_len()
3234 end += (1 << trans->dbg.dest_tlv->end_shift); in iwl_trans_get_fw_monitor_len()
3246 *iwl_trans_pcie_dump_data(struct iwl_trans *trans, in iwl_trans_pcie_dump_data() argument
3249 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_dump_data()
3251 struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; in iwl_trans_pcie_dump_data()
3256 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && in iwl_trans_pcie_dump_data()
3257 !trans->trans_cfg->mq_rx_supported && in iwl_trans_pcie_dump_data()
3274 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); in iwl_trans_pcie_dump_data()
3282 if (trans->trans_cfg->gen2) in iwl_trans_pcie_dump_data()
3284 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - in iwl_trans_pcie_dump_data()
3285 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); in iwl_trans_pcie_dump_data()
3297 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) in iwl_trans_pcie_dump_data()
3306 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) in iwl_trans_pcie_dump_data()
3307 for (i = 0; i < trans->init_dram.paging_cnt; i++) in iwl_trans_pcie_dump_data()
3310 trans->init_dram.paging[i].size; in iwl_trans_pcie_dump_data()
3320 u16 tfd_size = trans->txqs.tfd.size; in iwl_trans_pcie_dump_data()
3331 if (trans->trans_cfg->use_tfh) in iwl_trans_pcie_dump_data()
3336 cmdlen = iwl_trans_pcie_get_cmdlen(trans, in iwl_trans_pcie_dump_data()
3350 ptr = iwl_txq_dec_wrap(trans, ptr); in iwl_trans_pcie_dump_data()
3360 len += iwl_trans_pcie_dump_csr(trans, &data); in iwl_trans_pcie_dump_data()
3362 len += iwl_trans_pcie_fh_regs_dump(trans, &data); in iwl_trans_pcie_dump_data()
3364 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); in iwl_trans_pcie_dump_data()
3367 if (trans->trans_cfg->gen2 && in iwl_trans_pcie_dump_data()
3369 for (i = 0; i < trans->init_dram.paging_cnt; i++) { in iwl_trans_pcie_dump_data()
3371 u32 page_len = trans->init_dram.paging[i].size; in iwl_trans_pcie_dump_data()
3378 trans->init_dram.paging[i].block, page_len); in iwl_trans_pcie_dump_data()
3385 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); in iwl_trans_pcie_dump_data()
3393 static int iwl_trans_pcie_suspend(struct iwl_trans *trans) in iwl_trans_pcie_suspend() argument
3398 static void iwl_trans_pcie_resume(struct iwl_trans *trans) in iwl_trans_pcie_resume() argument
3489 struct iwl_trans *trans; in iwl_trans_pcie_alloc() local
3500 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, in iwl_trans_pcie_alloc()
3502 if (!trans) in iwl_trans_pcie_alloc()
3505 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_alloc()
3507 trans_pcie->trans = trans; in iwl_trans_pcie_alloc()
3540 addr_size = trans->txqs.tfd.addr_size; in iwl_trans_pcie_alloc()
3575 iwl_disable_interrupts(trans); in iwl_trans_pcie_alloc()
3577 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); in iwl_trans_pcie_alloc()
3578 if (trans->hw_rev == 0xffffffff) { in iwl_trans_pcie_alloc()
3591 trans->hw_rev = (trans->hw_rev & 0xfff0) | in iwl_trans_pcie_alloc()
3592 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); in iwl_trans_pcie_alloc()
3594 ret = iwl_pcie_prepare_card_hw(trans); in iwl_trans_pcie_alloc()
3596 IWL_WARN(trans, "Exit HW not ready\n"); in iwl_trans_pcie_alloc()
3604 ret = iwl_finish_nic_init(trans, cfg_trans); in iwl_trans_pcie_alloc()
3610 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); in iwl_trans_pcie_alloc()
3612 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); in iwl_trans_pcie_alloc()
3613 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; in iwl_trans_pcie_alloc()
3614 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), in iwl_trans_pcie_alloc()
3628 ret = iwl_pcie_alloc_ict(trans); in iwl_trans_pcie_alloc()
3635 IRQF_SHARED, DRV_NAME, trans); in iwl_trans_pcie_alloc()
3637 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); in iwl_trans_pcie_alloc()
3648 iwl_dbg_tlv_init(trans); in iwl_trans_pcie_alloc()
3650 return trans; in iwl_trans_pcie_alloc()
3653 iwl_pcie_free_ict(trans); in iwl_trans_pcie_alloc()
3657 iwl_trans_free(trans); in iwl_trans_pcie_alloc()
3661 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) in iwl_trans_pcie_sync_nmi() argument
3663 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_sync_nmi()
3665 bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status); in iwl_trans_pcie_sync_nmi()
3680 iwl_disable_interrupts(trans); in iwl_trans_pcie_sync_nmi()
3682 iwl_force_nmi(trans); in iwl_trans_pcie_sync_nmi()
3684 u32 inta_hw = iwl_read32(trans, inta_addr); in iwl_trans_pcie_sync_nmi()
3689 iwl_write32(trans, inta_addr, inta_hw & sw_err_bit); in iwl_trans_pcie_sync_nmi()
3701 iwl_enable_interrupts(trans); in iwl_trans_pcie_sync_nmi()
3703 iwl_trans_fw_error(trans); in iwl_trans_pcie_sync_nmi()