251 		iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),  in iwl_pcie_rxq_inc_wr_ptr()
254 		iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);  in iwl_pcie_rxq_inc_wr_ptr()
926 	iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);  in iwl_pcie_rx_hw_init()
928 	iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);  in iwl_pcie_rx_hw_init()
929 	iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);  in iwl_pcie_rx_hw_init()
930 	iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);  in iwl_pcie_rx_hw_init()
933 	iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);  in iwl_pcie_rx_hw_init()
936 	iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,  in iwl_pcie_rx_hw_init()
940 	iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,  in iwl_pcie_rx_hw_init()
951 	iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,  in iwl_pcie_rx_hw_init()
1880 	iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);  in iwl_pcie_irq_handler()
1969 			iwl_write32(trans, CSR_FH_INT_STATUS,  in iwl_pcie_irq_handler()
1974 			iwl_write32(trans,  in iwl_pcie_irq_handler()
2012 		iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);  in iwl_pcie_irq_handler()
2119 	iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);  in iwl_pcie_reset_ict()
2122 	iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);  in iwl_pcie_reset_ict()
2149 	iwl_write32(trans, CSR_INT_MASK, 0x00000000);  in iwl_pcie_isr()
2175 	iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh);  in iwl_pcie_irq_msix_handler()
2176 	iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);  in iwl_pcie_irq_msix_handler()