Lines Matching refs:CSR_BASE
83 #define CSR_BASE (0x000) macro
85 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
86 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
87 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
88 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
89 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
90 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
91 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
92 #define CSR_GP_CNTRL (CSR_BASE+0x024)
95 #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
105 #define CSR_HW_REV (CSR_BASE+0x028)
116 #define CSR_HW_RF_ID (CSR_BASE+0x09c)
124 #define CSR_EEPROM_REG (CSR_BASE+0x02c)
125 #define CSR_EEPROM_GP (CSR_BASE+0x030)
126 #define CSR_OTP_GP_REG (CSR_BASE+0x034)
128 #define CSR_GIO_REG (CSR_BASE+0x03C)
129 #define CSR_GP_UCODE_REG (CSR_BASE+0x048)
130 #define CSR_GP_DRIVER_REG (CSR_BASE+0x050)
136 #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
137 #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
138 #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
139 #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
141 #define CSR_MBOX_SET_REG (CSR_BASE + 0x88)
143 #define CSR_LED_REG (CSR_BASE+0x094)
144 #define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
145 #define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE + 0x0A8) /* 6000 and up */
147 #define CSR_MAC_SHADOW_REG_CTL2 (CSR_BASE + 0x0AC)
151 #define CSR_LTR_LONG_VAL_AD (CSR_BASE + 0x0D4)
161 #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
164 #define CSR_HOST_CHICKEN (CSR_BASE + 0x204)
168 #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
173 #define CSR_MONITOR_CFG_REG (CSR_BASE+0x214)
174 #define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228)
185 #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
187 #define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
188 #define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)
508 #define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec)
509 #define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4)