Lines Matching refs:AR_CFG
1277 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1287 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1412 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); in ath9k_hw_set_reset()
1413 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK, in ath9k_hw_set_reset()
1415 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); in ath9k_hw_set_reset()
1648 if (REG_READ(ah, AR_CFG) == 0xdeadbeef) in ath9k_hw_check_alive()
1756 mask = REG_READ(ah, AR_CFG); in ath9k_hw_init_desc()
1762 REG_WRITE(ah, AR_CFG, mask); in ath9k_hw_init_desc()
1764 REG_READ(ah, AR_CFG)); in ath9k_hw_init_desc()
1770 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); in ath9k_hw_init_desc()
1772 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_init_desc()
1778 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); in ath9k_hw_init_desc()
1780 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_init_desc()