3406 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_tx_lock()
3427 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_tx_unlock()
3447 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_vif_tx_lock()
3458 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_vif_tx_unlock()
3478 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_vif_handle_tx_pause()
3523 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_handle_tx_pause_vdev()
3528 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_handle_tx_pause_vdev()
3563 	if (ar->htt.target_version_major < 3 &&  in ath10k_mac_tx_h_get_txmode()
3758 	return (ar->htt.target_version_major >= 3 &&  in ath10k_mac_tx_frm_has_freq()
3759 		ar->htt.target_version_minor >= 4 &&  in ath10k_mac_tx_frm_has_freq()
3801 		else if (ar->htt.target_version_major >= 3)  in ath10k_mac_tx_h_get_txpath()
3815 	struct ath10k_htt *htt = &ar->htt;  in ath10k_mac_tx_submit()  local
3820 		ret = ath10k_htt_tx(htt, txmode, skb);  in ath10k_mac_tx_submit()
3823 		ret = ath10k_htt_mgmt_tx(htt, skb);  in ath10k_mac_tx_submit()
4091 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_txq_unref()
4092 	idr_for_each_entry(&ar->htt.pending_tx, msdu, msdu_id) {  in ath10k_mac_txq_unref()
4097 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_txq_unref()
4130 	if (ar->htt.tx_q_state.mode == HTT_TX_MODE_SWITCH_PUSH)  in ath10k_mac_tx_can_push()
4133 	if (ar->htt.num_pending_tx < ar->htt.tx_q_state.num_push_allowed)  in ath10k_mac_tx_can_push()
4192 	struct ath10k_htt *htt = &ar->htt;  in ath10k_mac_tx_push_txq()  local
4205 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4206 	ret = ath10k_htt_tx_inc_pending(htt);  in ath10k_mac_tx_push_txq()
4207 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4214 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4215 		ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4216 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4233 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4234 		ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp);  in ath10k_mac_tx_push_txq()
4237 			ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4238 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4241 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4248 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4249 		ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4251 			ath10k_htt_tx_mgmt_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4252 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4257 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4259 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4291 	if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH)  in ath10k_mac_tx_push_pending()
4294 	if (ar->htt.num_pending_tx >= (ar->htt.max_num_pending_tx / 2))  in ath10k_mac_tx_push_pending()
4477 	struct ath10k_htt *htt = &ar->htt;  in ath10k_mac_op_tx()  local
4501 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4504 		ret = ath10k_htt_tx_inc_pending(htt);  in ath10k_mac_op_tx()
4508 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4513 		ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp);  in ath10k_mac_op_tx()
4517 			ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_op_tx()
4518 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4522 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4529 			spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4530 			ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_op_tx()
4532 				ath10k_htt_tx_mgmt_dec_pending(htt);  in ath10k_mac_op_tx()
4533 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4547 	if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH)  in ath10k_mac_op_wake_tx_queue()
5668 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_add_interface()
5671 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_add_interface()
5815 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_remove_interface()
5817 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_remove_interface()
7865 	time_left = wait_event_timeout(ar->htt.empty_tx_wq, ({  in ath10k_mac_wait_tx_complete()
7868 			spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_wait_tx_complete()
7869 			empty = (ar->htt.num_pending_tx == 0);  in ath10k_mac_wait_tx_complete()
7870 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_wait_tx_complete()
7899 			ath10k_htt_flush_tx(&ar->htt);  in ath10k_flush()
9136 	if (ar->htt.disable_tx_comp) {  in ath10k_sta_statistics()