1 // SPDX-License-Identifier: ISC
3  * Copyright (c) 2014-2017 Qualcomm Atheros, Inc.
10 #include "hw.h"
12 #include "wmi-ops.h"
555 	survey->filled |= SURVEY_INFO_TIME |  in ath10k_hw_fill_survey_time()
558 	wraparound_type = ar->hw_params.cc_wraparound_type;  in ath10k_hw_fill_survey_time()
565 				survey->filled &= ~SURVEY_INFO_TIME_BUSY;  in ath10k_hw_fill_survey_time()
580 	cc -= cc_prev - cc_fix;  in ath10k_hw_fill_survey_time()
581 	rcc -= rcc_prev - rcc_fix;  in ath10k_hw_fill_survey_time()
583 	survey->time = CCNT_TO_MSEC(ar, cc);  in ath10k_hw_fill_survey_time()
584 	survey->time_busy = CCNT_TO_MSEC(ar, rcc);  in ath10k_hw_fill_survey_time()
603 	mutex_lock(&ar->conf_mutex);  in ath10k_hw_qca988x_set_coverage_class()
606 	if ((ar->state != ATH10K_STATE_ON) &&  in ath10k_hw_qca988x_set_coverage_class()
607 	    (ar->state != ATH10K_STATE_RESTARTED)) {  in ath10k_hw_qca988x_set_coverage_class()
608 		spin_lock_bh(&ar->data_lock);  in ath10k_hw_qca988x_set_coverage_class()
610 		ar->fw_coverage.coverage_class = value;  in ath10k_hw_qca988x_set_coverage_class()
611 		spin_unlock_bh(&ar->data_lock);  in ath10k_hw_qca988x_set_coverage_class()
627 		value = ar->fw_coverage.coverage_class;  in ath10k_hw_qca988x_set_coverage_class()
632 	if (value == ar->fw_coverage.coverage_class &&  in ath10k_hw_qca988x_set_coverage_class()
633 	    slottime_reg == ar->fw_coverage.reg_slottime_conf &&  in ath10k_hw_qca988x_set_coverage_class()
634 	    timeout_reg == ar->fw_coverage.reg_ack_cts_timeout_conf &&  in ath10k_hw_qca988x_set_coverage_class()
635 	    phyclk_reg == ar->fw_coverage.reg_phyclk)  in ath10k_hw_qca988x_set_coverage_class()
639 	if (slottime_reg != ar->fw_coverage.reg_slottime_conf)  in ath10k_hw_qca988x_set_coverage_class()
640 		ar->fw_coverage.reg_slottime_orig = slottime_reg;  in ath10k_hw_qca988x_set_coverage_class()
641 	if (timeout_reg != ar->fw_coverage.reg_ack_cts_timeout_conf)  in ath10k_hw_qca988x_set_coverage_class()
642 		ar->fw_coverage.reg_ack_cts_timeout_orig = timeout_reg;  in ath10k_hw_qca988x_set_coverage_class()
643 	ar->fw_coverage.reg_phyclk = phyclk_reg;  in ath10k_hw_qca988x_set_coverage_class()
646 	slottime_reg = ar->fw_coverage.reg_slottime_orig;  in ath10k_hw_qca988x_set_coverage_class()
647 	timeout_reg = ar->fw_coverage.reg_ack_cts_timeout_orig;  in ath10k_hw_qca988x_set_coverage_class()
661 …	    "failed to set coverage class: expected slot time of 9 or 20us in HW register. It is %uus.\n",  in ath10k_hw_qca988x_set_coverage_class()
716 	spin_lock_bh(&ar->data_lock);  in ath10k_hw_qca988x_set_coverage_class()
717 	ar->fw_coverage.coverage_class = value;  in ath10k_hw_qca988x_set_coverage_class()
718 	spin_unlock_bh(&ar->data_lock);  in ath10k_hw_qca988x_set_coverage_class()
720 	ar->fw_coverage.reg_slottime_conf = slottime_reg;  in ath10k_hw_qca988x_set_coverage_class()
721 	ar->fw_coverage.reg_ack_cts_timeout_conf = timeout_reg;  in ath10k_hw_qca988x_set_coverage_class()
724 	mutex_unlock(&ar->conf_mutex);  in ath10k_hw_qca988x_set_coverage_class()
728  * ath10k_hw_qca6174_enable_pll_clock() - enable the qca6174 hw pll clock
744 	struct ath10k_hw_params *hw;  in ath10k_hw_qca6174_enable_pll_clock()  local
747 	hw = &ar->hw_params;  in ath10k_hw_qca6174_enable_pll_clock()
749 	if (ar->regs->core_clk_div_address == 0 ||  in ath10k_hw_qca6174_enable_pll_clock()
750 	    ar->regs->cpu_pll_init_address == 0 ||  in ath10k_hw_qca6174_enable_pll_clock()
751 	    ar->regs->cpu_speed_address == 0)  in ath10k_hw_qca6174_enable_pll_clock()
752 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
754 	clk_div_addr = ar->regs->core_clk_div_address;  in ath10k_hw_qca6174_enable_pll_clock()
755 	pll_init_addr = ar->regs->cpu_pll_init_address;  in ath10k_hw_qca6174_enable_pll_clock()
756 	speed_addr = ar->regs->cpu_speed_address;  in ath10k_hw_qca6174_enable_pll_clock()
758 	/* Read efuse register to find out the right hw clock configuration */  in ath10k_hw_qca6174_enable_pll_clock()
762 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
764 	/* sanitize if the hw refclk index is out of the boundary */  in ath10k_hw_qca6174_enable_pll_clock()
766 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
768 	hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)];  in ath10k_hw_qca6174_enable_pll_clock()
774 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
777 	reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) |  in ath10k_hw_qca6174_enable_pll_clock()
778 		    SM(hw_clk->outdiv, BB_PLL_CONFIG_OUTDIV));  in ath10k_hw_qca6174_enable_pll_clock()
781 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
783 	/* Set the correct settle time value to pll_settle register */  in ath10k_hw_qca6174_enable_pll_clock()
787 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
790 	reg_val |= SM(hw_clk->settle_time, WLAN_PLL_SETTLE_TIME);  in ath10k_hw_qca6174_enable_pll_clock()
793 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
799 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
805 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
812 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
818 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
820 	reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) |  in ath10k_hw_qca6174_enable_pll_clock()
821 		    SM(hw_clk->div, WLAN_PLL_CONTROL_DIV) |  in ath10k_hw_qca6174_enable_pll_clock()
825 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
833 			return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
838 		wait_limit--;  in ath10k_hw_qca6174_enable_pll_clock()
844 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
850 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
856 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
864 			return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
869 		wait_limit--;  in ath10k_hw_qca6174_enable_pll_clock()
875 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
881 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
887 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
893 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
898 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
905 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
908 	ret = ath10k_bmi_write_memory(ar, speed_addr, &hw->target_cpu_freq,  in ath10k_hw_qca6174_enable_pll_clock()
909 				      sizeof(hw->target_cpu_freq));  in ath10k_hw_qca6174_enable_pll_clock()
911 		return -EINVAL;  in ath10k_hw_qca6174_enable_pll_clock()
946 		size = REGION_ACCESS_SIZE_LIMIT - addr;  in ath10k_hw_diag_segment_msb_download()
947 		remain_size = length - size;  in ath10k_hw_diag_segment_msb_download()
1017 		return -EINVAL;  in ath10k_hw_diag_fast_download()
1023 	if (__le32_to_cpu(hdr->magic_num) != BMI_SGMTFILE_MAGIC_NUM) {  in ath10k_hw_diag_fast_download()
1026 			   hdr->magic_num);  in ath10k_hw_diag_fast_download()
1027 		return -EINVAL;  in ath10k_hw_diag_fast_download()
1030 	if (hdr->file_flags != 0) {  in ath10k_hw_diag_fast_download()
1033 			   hdr->file_flags);  in ath10k_hw_diag_fast_download()
1034 		return -EINVAL;  in ath10k_hw_diag_fast_download()
1037 	metadata = (struct bmi_segmented_metadata *)hdr->data;  in ath10k_hw_diag_fast_download()
1038 	left = length - sizeof(*hdr);  in ath10k_hw_diag_fast_download()
1044 			ret = -EINVAL;  in ath10k_hw_diag_fast_download()
1047 		base_addr = __le32_to_cpu(metadata->addr);  in ath10k_hw_diag_fast_download()
1048 		base_len = __le32_to_cpu(metadata->length);  in ath10k_hw_diag_fast_download()
1049 		buf = metadata->data;  in ath10k_hw_diag_fast_download()
1050 		left -= sizeof(*metadata);  in ath10k_hw_diag_fast_download()
1069 			ret = -EINVAL;  in ath10k_hw_diag_fast_download()
1077 				ret = -EINVAL;  in ath10k_hw_diag_fast_download()
1097 		left -= base_len;  in ath10k_hw_diag_fast_download()
1108 	return (resp->data_tx_completion.flags2 & HTT_TX_CMPL_FLAG_DATA_RSSI);  in ath10k_htt_tx_rssi_enable()
1113 	return (resp->data_tx_completion.flags2 &  in ath10k_htt_tx_rssi_enable_wcn3990()
1122 	if (resp->data_tx_completion.flags2 & HTT_TX_DATA_APPEND_RETRIES)  in ath10k_get_htt_tx_data_rssi_pad()
1126 	if (resp->data_tx_completion.flags2 & HTT_TX_DATA_APPEND_TIMESTAMP)  in ath10k_get_htt_tx_data_rssi_pad()
1139 	return MS(__le32_to_cpu(rxd->msdu_end.qca99x0.info1),  in ath10k_qca99x0_rx_desc_get_l3_pad_bytes()
1145 	return !!(rxd->msdu_end.common.info0 &  in ath10k_qca99x0_rx_desc_msdu_limit_error()