Lines Matching +full:0 +full:xcd00
43 #define PLA_IDR 0xc000
44 #define PLA_RCR 0xc010
45 #define PLA_RMS 0xc016
46 #define PLA_RXFIFO_CTRL0 0xc0a0
47 #define PLA_RXFIFO_CTRL1 0xc0a4
48 #define PLA_RXFIFO_CTRL2 0xc0a8
49 #define PLA_DMY_REG0 0xc0b0
50 #define PLA_FMC 0xc0b4
51 #define PLA_CFG_WOL 0xc0b6
52 #define PLA_TEREDO_CFG 0xc0bc
53 #define PLA_TEREDO_WAKE_BASE 0xc0c4
54 #define PLA_MAR 0xcd00
55 #define PLA_BACKUP 0xd000
56 #define PLA_BDC_CR 0xd1a0
57 #define PLA_TEREDO_TIMER 0xd2cc
58 #define PLA_REALWOW_TIMER 0xd2e8
59 #define PLA_UPHY_TIMER 0xd388
60 #define PLA_SUSPEND_FLAG 0xd38a
61 #define PLA_INDICATE_FALG 0xd38c
62 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
63 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
64 #define PLA_EXTRA_STATUS 0xd398
65 #define PLA_EFUSE_DATA 0xdd00
66 #define PLA_EFUSE_CMD 0xdd02
67 #define PLA_LEDSEL 0xdd90
68 #define PLA_LED_FEATURE 0xdd92
69 #define PLA_PHYAR 0xde00
70 #define PLA_BOOT_CTRL 0xe004
71 #define PLA_LWAKE_CTRL_REG 0xe007
72 #define PLA_GPHY_INTR_IMR 0xe022
73 #define PLA_EEE_CR 0xe040
74 #define PLA_EEEP_CR 0xe080
75 #define PLA_MAC_PWR_CTRL 0xe0c0
76 #define PLA_MAC_PWR_CTRL2 0xe0ca
77 #define PLA_MAC_PWR_CTRL3 0xe0cc
78 #define PLA_MAC_PWR_CTRL4 0xe0ce
79 #define PLA_WDT6_CTRL 0xe428
80 #define PLA_TCR0 0xe610
81 #define PLA_TCR1 0xe612
82 #define PLA_MTPS 0xe615
83 #define PLA_TXFIFO_CTRL 0xe618
84 #define PLA_RSTTALLY 0xe800
85 #define PLA_CR 0xe813
86 #define PLA_CRWECR 0xe81c
87 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
88 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
89 #define PLA_CONFIG5 0xe822
90 #define PLA_PHY_PWR 0xe84c
91 #define PLA_OOB_CTRL 0xe84f
92 #define PLA_CPCR 0xe854
93 #define PLA_MISC_0 0xe858
94 #define PLA_MISC_1 0xe85a
95 #define PLA_OCP_GPHY_BASE 0xe86c
96 #define PLA_TALLYCNT 0xe890
97 #define PLA_SFF_STS_7 0xe8de
98 #define PLA_PHYSTATUS 0xe908
99 #define PLA_CONFIG6 0xe90a /* CONFIG6 */
100 #define PLA_BP_BA 0xfc26
101 #define PLA_BP_0 0xfc28
102 #define PLA_BP_1 0xfc2a
103 #define PLA_BP_2 0xfc2c
104 #define PLA_BP_3 0xfc2e
105 #define PLA_BP_4 0xfc30
106 #define PLA_BP_5 0xfc32
107 #define PLA_BP_6 0xfc34
108 #define PLA_BP_7 0xfc36
109 #define PLA_BP_EN 0xfc38
111 #define USB_USB2PHY 0xb41e
112 #define USB_SSPHYLINK1 0xb426
113 #define USB_SSPHYLINK2 0xb428
114 #define USB_U2P3_CTRL 0xb460
115 #define USB_CSR_DUMMY1 0xb464
116 #define USB_CSR_DUMMY2 0xb466
117 #define USB_DEV_STAT 0xb808
118 #define USB_CONNECT_TIMER 0xcbf8
119 #define USB_MSC_TIMER 0xcbfc
120 #define USB_BURST_SIZE 0xcfc0
121 #define USB_FW_FIX_EN0 0xcfca
122 #define USB_FW_FIX_EN1 0xcfcc
123 #define USB_LPM_CONFIG 0xcfd8
124 #define USB_CSTMR 0xcfef /* RTL8153A */
125 #define USB_FW_CTRL 0xd334 /* RTL8153B */
126 #define USB_FC_TIMER 0xd340
127 #define USB_USB_CTRL 0xd406
128 #define USB_PHY_CTRL 0xd408
129 #define USB_TX_AGG 0xd40a
130 #define USB_RX_BUF_TH 0xd40c
131 #define USB_USB_TIMER 0xd428
132 #define USB_RX_EARLY_TIMEOUT 0xd42c
133 #define USB_RX_EARLY_SIZE 0xd42e
134 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
135 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
136 #define USB_TX_DMA 0xd434
137 #define USB_UPT_RXDMA_OWN 0xd437
138 #define USB_TOLERANCE 0xd490
139 #define USB_LPM_CTRL 0xd41a
140 #define USB_BMU_RESET 0xd4b0
141 #define USB_U1U2_TIMER 0xd4da
142 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
143 #define USB_UPS_CTRL 0xd800
144 #define USB_POWER_CUT 0xd80a
145 #define USB_MISC_0 0xd81a
146 #define USB_MISC_1 0xd81f
147 #define USB_AFE_CTRL2 0xd824
148 #define USB_UPS_CFG 0xd842
149 #define USB_UPS_FLAGS 0xd848
150 #define USB_WDT1_CTRL 0xe404
151 #define USB_WDT11_CTRL 0xe43c
162 #define USB_BP_8 0xfc38 /* RTL8153B */
163 #define USB_BP_9 0xfc3a
164 #define USB_BP_10 0xfc3c
165 #define USB_BP_11 0xfc3e
166 #define USB_BP_12 0xfc40
167 #define USB_BP_13 0xfc42
168 #define USB_BP_14 0xfc44
169 #define USB_BP_15 0xfc46
170 #define USB_BP2_EN 0xfc48
173 #define OCP_ALDPS_CONFIG 0x2010
174 #define OCP_EEE_CONFIG1 0x2080
175 #define OCP_EEE_CONFIG2 0x2092
176 #define OCP_EEE_CONFIG3 0x2094
177 #define OCP_BASE_MII 0xa400
178 #define OCP_EEE_AR 0xa41a
179 #define OCP_EEE_DATA 0xa41c
180 #define OCP_PHY_STATUS 0xa420
181 #define OCP_NCTL_CFG 0xa42c
182 #define OCP_POWER_CFG 0xa430
183 #define OCP_EEE_CFG 0xa432
184 #define OCP_SRAM_ADDR 0xa436
185 #define OCP_SRAM_DATA 0xa438
186 #define OCP_DOWN_SPEED 0xa442
187 #define OCP_EEE_ABLE 0xa5c4
188 #define OCP_EEE_ADV 0xa5d0
189 #define OCP_EEE_LPABLE 0xa5d2
190 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
191 #define OCP_PHY_PATCH_STAT 0xb800
192 #define OCP_PHY_PATCH_CMD 0xb820
193 #define OCP_PHY_LOCK 0xb82e
194 #define OCP_ADC_IOFFSET 0xbcfc
195 #define OCP_ADC_CFG 0xbc06
196 #define OCP_SYSCLK_CFG 0xc416
199 #define SRAM_GREEN_CFG 0x8011
200 #define SRAM_LPF_CFG 0x8012
201 #define SRAM_10M_AMP1 0x8080
202 #define SRAM_10M_AMP2 0x8082
203 #define SRAM_IMPEDANCE 0x8084
204 #define SRAM_PHY_LOCK 0xb82e
207 #define RCR_AAP 0x00000001
208 #define RCR_APM 0x00000002
209 #define RCR_AM 0x00000004
210 #define RCR_AB 0x00000008
214 #define RXFIFO_THR1_NORMAL 0x00080002
215 #define RXFIFO_THR1_OOB 0x01800003
218 #define RXFIFO_THR2_FULL 0x00000060
219 #define RXFIFO_THR2_HIGH 0x00000038
220 #define RXFIFO_THR2_OOB 0x0000004a
221 #define RXFIFO_THR2_NORMAL 0x00a0
224 #define RXFIFO_THR3_FULL 0x00000078
225 #define RXFIFO_THR3_HIGH 0x00000048
226 #define RXFIFO_THR3_OOB 0x0000005a
227 #define RXFIFO_THR3_NORMAL 0x0110
230 #define TXFIFO_THR_NORMAL 0x00400008
231 #define TXFIFO_THR_NORMAL2 0x01000008
234 #define ECM_ALDPS 0x0002
237 #define FMC_FCR_MCU_EN 0x0001
240 #define EEEP_CR_EEEP_TX 0x0002
243 #define WDT6_SET_MODE 0x0010
246 #define TCR0_TX_EMPTY 0x0800
247 #define TCR0_AUTO_FIFO 0x0080
250 #define VERSION_MASK 0x7cf0
257 #define TALLY_RESET 0x0001
260 #define CR_RST 0x10
261 #define CR_RE 0x08
262 #define CR_TE 0x04
265 #define CRWECR_NORAML 0x00
266 #define CRWECR_CONFIG 0xc0
269 #define NOW_IS_OOB 0x80
270 #define TXFIFO_EMPTY 0x20
271 #define RXFIFO_EMPTY 0x10
272 #define LINK_LIST_READY 0x02
273 #define DIS_MCU_CLROOB 0x01
277 #define RXDY_GATED_EN 0x0008
280 #define RE_INIT_LL 0x8000
281 #define MCU_BORW_EN 0x4000
284 #define CPCR_RX_VLAN 0x0040
287 #define MAGIC_EN 0x0001
290 #define TEREDO_SEL 0x8000
291 #define TEREDO_WAKE_MASK 0x7f00
292 #define TEREDO_RS_EVENT_MASK 0x00fe
293 #define OOB_TEREDO_EN 0x0001
296 #define ALDPS_PROXY_MODE 0x0001
303 #define LINK_ON_WAKE_EN 0x0010
304 #define LINK_OFF_WAKE_EN 0x0008
307 #define LANWAKE_CLR_EN BIT(0)
310 #define BWF_EN 0x0040
311 #define MWF_EN 0x0020
312 #define UWF_EN 0x0010
313 #define LAN_WAKE_EN 0x0002
316 #define LED_MODE_MASK 0x0700
319 #define TX_10M_IDLE_EN 0x0080
320 #define PFM_PWM_SWITCH 0x0040
324 #define D3_CLK_GATED_EN 0x00004000
325 #define MCU_CLK_RATIO 0x07010f07
326 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
327 #define ALDPS_SPDWN_RATIO 0x0f87
330 #define EEE_SPDWN_RATIO 0x8007
335 #define PKT_AVAIL_SPDWN_EN 0x0100
336 #define SUSPEND_SPDWN_EN 0x0004
337 #define U1U2_SPDWN_EN 0x0002
338 #define L1_SPDWN_EN 0x0001
341 #define PWRSAVE_SPDWN_EN 0x1000
342 #define RXDV_SPDWN_EN 0x0800
343 #define TX10MIDLE_EN 0x0100
344 #define TP100_SPDWN_EN 0x0020
345 #define TP500_SPDWN_EN 0x0010
346 #define TP1000_SPDWN_EN 0x0008
347 #define EEE_SPDWN_EN 0x0001
350 #define GPHY_STS_MSK 0x0001
351 #define SPEED_DOWN_MSK 0x0002
352 #define SPDWN_RXDV_MSK 0x0004
353 #define SPDWN_LINKCHG_MSK 0x0008
356 #define PHYAR_FLAG 0x80000000
359 #define EEE_RX_EN 0x0001
360 #define EEE_TX_EN 0x0002
363 #define AUTOLOAD_DONE 0x0002
369 #define LINK_CHG_EVENT BIT(0)
372 #define UPCOMING_RUNTIME_D3 BIT(0)
375 #define DEBUG_OE BIT(0)
376 #define DEBUG_LTSSM 0x0082
382 #define POLL_LINK_CHG BIT(0)
385 #define USB2PHY_SUSPEND 0x0001
386 #define USB2PHY_L1 0x0002
392 #define pwd_dn_scale_mask 0x3ffe
396 #define DYNAMIC_BURST 0x0001
399 #define EP4_FULL_FC 0x0001
402 #define STAT_SPEED_MASK 0x0006
403 #define STAT_SPEED_HIGH 0x0000
404 #define STAT_SPEED_FULL 0x0002
413 #define LPM_U1U2_EN BIT(0)
416 #define TX_AGG_MAX_THRESHOLD 0x03
419 #define RX_THR_SUPPER 0x0c350180
420 #define RX_THR_HIGH 0x7a120180
421 #define RX_THR_SLOW 0xffff0180
422 #define RX_THR_B 0x00010001
425 #define TEST_MODE_DISABLE 0x00000001
426 #define TX_SIZE_ADJUST1 0x00000100
429 #define BMU_RESET_EP_IN 0x01
430 #define BMU_RESET_EP_OUT 0x02
433 #define OWN_UPDATE BIT(0)
440 #define POWER_CUT 0x0100
443 #define RESUME_INDICATE 0x0001
446 #define FORCE_SUPER BIT(0)
455 #define RX_AGG_DISABLE 0x0010
456 #define RX_ZERO_EN 0x0080
459 #define U2P3_ENABLE 0x0001
462 #define PWR_EN 0x0001
463 #define PHASE2_EN 0x0008
468 #define PCUT_STATUS 0x0001
476 #define WTD1_EN BIT(0)
479 #define TIMER11_EN 0x0001
483 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
485 #define LPM_TIMER_MASK 0x0c
486 #define LPM_TIMER_500MS 0x04 /* 500 ms */
487 #define LPM_TIMER_500US 0x0c /* 500 us */
488 #define ROK_EXIT_LPM 0x02
491 #define SEN_VAL_MASK 0xf800
492 #define SEN_VAL_NORMAL 0xa000
493 #define SEL_RXIDLE 0x0100
496 #define SAW_CNT_1MS_MASK 0x0fff
499 #define UPS_FLAGS_R_TUNE BIT(0)
527 #define ENPWRSAVE 0x8000
528 #define ENPDNPS 0x0200
529 #define LINKENA 0x0100
530 #define DIS_SDSAVE 0x0010
533 #define PHY_STAT_MASK 0x0007
542 #define EEE_CLKDIV_EN 0x8000
543 #define EN_ALDPS 0x0004
544 #define EN_10M_PLLOFF 0x0001
547 #define RG_TXLPI_MSK_HFDUP 0x8000
548 #define RG_MATCLR_EN 0x4000
549 #define EEE_10_CAP 0x2000
550 #define EEE_NWAY_EN 0x1000
551 #define TX_QUIET_EN 0x0200
552 #define RX_QUIET_EN 0x0100
553 #define sd_rise_time_mask 0x0070
555 #define RG_RXLPI_MSK_HFDUP 0x0008
556 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
559 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
560 #define RG_DACQUIET_EN 0x0400
561 #define RG_LDVQUIET_EN 0x0200
562 #define RG_CKRSEL 0x0020
563 #define RG_EEEPRG_EN 0x0010
566 #define fast_snr_mask 0xff80
567 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
568 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
569 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
573 #define FUN_ADDR 0x0000
574 #define FUN_DATA 0x4000
575 /* bit[4:0] device addr */
578 #define CTAP_SHORT_EN 0x0040
579 #define EEE10_EN 0x0010
586 #define EN_10M_BGOFF 0x0080
589 #define TXDIS_STATE 0x01
590 #define ABD_STATE 0x02
599 #define PATCH_LOCK BIT(0)
602 #define CKADSEL_L 0x0100
603 #define ADC_EN 0x0080
604 #define EN_EMI_L 0x0040
614 #define LPF_AUTO_TUNE 0x8000
617 #define GDAC_IB_UPALL 0x0008
620 #define AMP_DN 0x0200
623 #define RX_DRIVING_MASK 0x6000
626 #define PHY_PATCH_LOCK 0x0001
629 #define AD_MASK 0xfee0
630 #define BND_MASK 0x0004
631 #define BD_MASK 0x0001
632 #define EFUSE 0xcfdb
633 #define PASS_THRU_MASK 0x1
635 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
638 _1000bps = 0x10,
639 _100bps = 0x08,
640 _10bps = 0x04,
641 LINK_STATUS = 0x02,
642 FULL_DUP = 0x01,
654 #define INTR_LINK 0x0004
656 #define RTL8152_REQT_READ 0xc0
657 #define RTL8152_REQT_WRITE 0x40
658 #define RTL8152_REQ_GET_REGS 0x05
659 #define RTL8152_REQ_SET_REGS 0x05
661 #define BYTE_EN_DWORD 0xff
662 #define BYTE_EN_WORD 0x33
663 #define BYTE_EN_BYTE 0x11
664 #define BYTE_EN_SIX_BYTES 0x3f
665 #define BYTE_EN_START_MASK 0x0f
666 #define BYTE_EN_END_MASK 0xf0
680 RTL8152_UNPLUG = 0,
693 #define VENDOR_ID_REALTEK 0x0bda
694 #define VENDOR_ID_MICROSOFT 0x045e
695 #define VENDOR_ID_SAMSUNG 0x04e8
696 #define VENDOR_ID_LENOVO 0x17ef
697 #define VENDOR_ID_LINKSYS 0x13b1
698 #define VENDOR_ID_NVIDIA 0x0955
699 #define VENDOR_ID_TPLINK 0x2357
701 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
702 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
704 #define MCU_TYPE_PLA 0x0100
705 #define MCU_TYPE_USB 0x0000
725 #define RX_LEN_MASK 0x7fff
751 #define GTTCPHO_MAX 0x7fU
752 #define TX_LEN_MAX 0x3ffffU
760 #define MSS_MAX 0x7ffU
762 #define TCPHO_MAX 0x7ffU
989 RTL_FW_END = 0,
998 RTL_VER_UNKNOWN = 0,
1012 TX_CSUM_SUCCESS = 0,
1017 #define RTL_ADVERTISED_10_HALF BIT(0)
1043 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), in get_registers()
1046 if (ret < 0) in get_registers()
1047 memset(data, 0xff, size); in get_registers()
1066 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), in set_registers()
1087 int ret = 0; in generic_ocp_read()
1096 if ((u32)index + (u32)size > 0xffff) in generic_ocp_read()
1102 if (ret < 0) in generic_ocp_read()
1110 if (ret < 0) in generic_ocp_read()
1115 size = 0; in generic_ocp_read()
1140 if ((u32)index + (u32)size > 0xffff) in generic_ocp_write()
1148 if (ret < 0) in generic_ocp_write()
1163 if (ret < 0) in generic_ocp_write()
1173 if (ret < 0) in generic_ocp_write()
1178 size = 0; in generic_ocp_write()
1185 if (ret < 0) in generic_ocp_write()
1244 data &= 0xffff; in ocp_read_word()
1251 u32 mask = 0xffff; in ocp_write_word()
1282 data &= 0xff; in ocp_read_byte()
1289 u32 mask = 0xff; in ocp_write_byte()
1312 ocp_base = addr & 0xf000; in ocp_reg_read()
1318 ocp_index = (addr & 0x0fff) | 0xb000; in ocp_reg_read()
1326 ocp_base = addr & 0xf000; in ocp_reg_write()
1332 ocp_index = (addr & 0x0fff) | 0xb000; in ocp_reg_write()
1401 if (ret < 0) in rtl8152_set_mac_address()
1438 mac_strlen = 0x16; in vendor_mac_passthru_addr_read()
1442 if ((ocp_data & AD_MASK) == 0x1000) { in vendor_mac_passthru_addr_read()
1453 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) { in vendor_mac_passthru_addr_read()
1462 mac_strlen = 0x17; in vendor_mac_passthru_addr_read()
1477 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || in vendor_mac_passthru_addr_read()
1478 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { in vendor_mac_passthru_addr_read()
1484 if (!(ret == 0 && is_valid_ether_addr(buf))) { in vendor_mac_passthru_addr_read()
1508 if (ret < 0) { in determine_ethernet_addr()
1516 if (ret < 0) in determine_ethernet_addr()
1522 if (ret < 0) { in determine_ethernet_addr()
1531 return 0; in determine_ethernet_addr()
1544 if (ret < 0) in set_ethernet_addr()
1587 case 0: in read_bulk_callback()
1680 case 0: /* success */ in intr_callback()
1701 if (INTR_LINK & __le16_to_cpu(d[0])) { in intr_callback()
1704 schedule_delayed_work(&tp->schedule, 0); in intr_callback()
1710 schedule_delayed_work(&tp->schedule, 0); in intr_callback()
1764 rx_agg->urb = usb_alloc_urb(0, mflags); in alloc_rx_agg()
1802 for (i = 0; i < RTL8152_MAX_TX; i++) { in free_all_mem()
1835 atomic_set(&tp->rx_count, 0); in alloc_all_mem()
1837 for (i = 0; i < RTL8152_MAX_RX; i++) { in alloc_all_mem()
1842 for (i = 0; i < RTL8152_MAX_TX; i++) { in alloc_all_mem()
1858 urb = usb_alloc_urb(0, GFP_KERNEL); in alloc_all_mem()
1873 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); in alloc_all_mem()
1886 return 0; in alloc_all_mem()
1941 if (skb_checksum_help(skb) < 0) in r8152_csum_workaround()
1971 swab16(opts2 & 0xffff)); in rtl_rx_vlan_tag()
1978 u32 opts1, opts2 = 0; in r8152_tx_csum()
1988 "Invalid transport offset 0x%x for TSO\n", in r8152_tx_csum()
2000 if (skb_cow_head(skb, 0)) { in r8152_tx_csum()
2020 "Invalid transport offset 0x%x\n", in r8152_tx_csum()
2071 agg->skb_num = 0; in r8152_tx_agg_fill()
2072 agg->skb_len = 0; in r8152_tx_agg_fill()
2107 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { in r8152_tx_agg_fill()
2143 if (ret < 0) in r8152_tx_agg_fill()
2151 if (ret < 0) in r8152_tx_agg_fill()
2231 int ret = 0, work_done = 0; in rx_bottom()
2263 int len_used = 0; in rx_bottom()
2318 skb_add_rx_frag(skb, 0, agg->page, in rx_bottom()
2361 urb->actual_length = 0; in rx_bottom()
2410 } while (res == 0); in tx_bottom()
2461 return 0; in r8152_submit_rx()
2475 urb->actual_length = 0; in r8152_submit_rx()
2524 schedule_delayed_work(&tp->schedule, 0); in rtl8152_set_rx_mode()
2544 mc_filter[1] = 0xffffffff; in _rtl8152_set_rx_mode()
2545 mc_filter[0] = 0xffffffff; in _rtl8152_set_rx_mode()
2550 mc_filter[1] = 0xffffffff; in _rtl8152_set_rx_mode()
2551 mc_filter[0] = 0xffffffff; in _rtl8152_set_rx_mode()
2555 mc_filter[1] = 0; in _rtl8152_set_rx_mode()
2556 mc_filter[0] = 0; in _rtl8152_set_rx_mode()
2565 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); in _rtl8152_set_rx_mode()
2566 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); in _rtl8152_set_rx_mode()
2601 schedule_delayed_work(&tp->schedule, 0); in rtl8152_start_xmit()
2630 for (i = 0; i < 1000; i++) { in rtl8152_nic_reset()
2684 int ret = 0, i = 0; in rtl_start_rx()
2705 } else if (unlikely(ret < 0)) { in rtl_start_rx()
2759 return 0; in rtl_stop_rx()
2789 return 0; in rtl_enable()
2895 for (i = 0; i < RTL8152_MAX_TX; i++) in rtl_disable()
2900 for (i = 0; i < 1000; i++) { in rtl_disable()
2907 for (i = 0; i < 1000; i++) { in rtl_disable()
2954 if (ret < 0) in rtl8152_set_features()
2979 u32 wolopts = 0; in __rtl_get_wol()
3052 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); in r8153_mac_clk_spd()
3053 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); in r8153_mac_clk_spd()
3054 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); in r8153_mac_clk_spd()
3055 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); in r8153_mac_clk_spd()
3064 memset(u1u2, 0xff, sizeof(u1u2)); in r8153_u1u2en()
3066 memset(u1u2, 0x00, sizeof(u1u2)); in r8153_u1u2en()
3098 u32 ups_flags = 0; in r8153b_ups_flags()
3173 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ in r8153b_green_en()
3174 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ in r8153b_green_en()
3175 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ in r8153b_green_en()
3177 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ in r8153b_green_en()
3178 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ in r8153b_green_en()
3179 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ in r8153b_green_en()
3194 for (i = 0; i < 500; i++) { in r8153_phy_status()
3223 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); in r8153b_ups_en()
3224 ocp_data |= BIT(0); in r8153b_ups_en()
3225 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); in r8153b_ups_en()
3232 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); in r8153b_ups_en()
3233 ocp_data &= ~BIT(0); in r8153b_ups_en()
3234 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); in r8153b_ups_en()
3240 data = r8153_phy_status(tp, 0); in r8153b_ups_en()
3416 /* The bit 0 ~ 7 are relative with teredo settings. They are in r8153_teredo_off()
3419 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); in r8153_teredo_off()
3427 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); in r8153_teredo_off()
3428 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); in r8153_teredo_off()
3454 ocp_write_byte(tp, type, PLA_BP_EN, 0); in rtl_clear_bp()
3460 ocp_write_byte(tp, MCU_TYPE_USB, USB_BP2_EN, 0); in rtl_clear_bp()
3462 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0); in rtl_clear_bp()
3463 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0); in rtl_clear_bp()
3464 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0); in rtl_clear_bp()
3465 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0); in rtl_clear_bp()
3466 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0); in rtl_clear_bp()
3467 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0); in rtl_clear_bp()
3468 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0); in rtl_clear_bp()
3469 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0); in rtl_clear_bp()
3471 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0); in rtl_clear_bp()
3476 ocp_write_word(tp, type, PLA_BP_0, 0); in rtl_clear_bp()
3477 ocp_write_word(tp, type, PLA_BP_1, 0); in rtl_clear_bp()
3478 ocp_write_word(tp, type, PLA_BP_2, 0); in rtl_clear_bp()
3479 ocp_write_word(tp, type, PLA_BP_3, 0); in rtl_clear_bp()
3480 ocp_write_word(tp, type, PLA_BP_4, 0); in rtl_clear_bp()
3481 ocp_write_word(tp, type, PLA_BP_5, 0); in rtl_clear_bp()
3482 ocp_write_word(tp, type, PLA_BP_6, 0); in rtl_clear_bp()
3483 ocp_write_word(tp, type, PLA_BP_7, 0); in rtl_clear_bp()
3487 ocp_write_word(tp, type, PLA_BP_BA, 0); in rtl_clear_bp()
3502 for (i = 0; request && i < 5000; i++) { in r8153_patch_request()
3513 return 0; in r8153_patch_request()
3527 return 0; in r8153_pre_ram_code()
3534 sram_write(tp, 0x0000, 0x0000); in r8153_post_ram_code()
3540 sram_write(tp, key_addr, 0x0000); in r8153_post_ram_code()
3546 return 0; in r8153_post_ram_code()
3559 fw_reg = 0xa014; in rtl8152_is_fw_phy_nc_ok()
3560 ba_reg = 0xa012; in rtl8152_is_fw_phy_nc_ok()
3561 patch_en_addr = 0xa01a; in rtl8152_is_fw_phy_nc_ok()
3562 mode_reg = 0xb820; in rtl8152_is_fw_phy_nc_ok()
3563 bp_start = 0xa000; in rtl8152_is_fw_phy_nc_ok()
3638 fw_reg = 0xf800; in rtl8152_is_fw_mac_ok()
3640 bp_en_addr = 0; in rtl8152_is_fw_mac_ok()
3650 fw_reg = 0xf800; in rtl8152_is_fw_mac_ok()
3665 fw_reg = 0xf800; in rtl8152_is_fw_mac_ok()
3673 fw_reg = 0xe600; in rtl8152_is_fw_mac_ok()
3758 alg = crypto_alloc_shash("sha256", 0, 0); in rtl8152_fw_verify_checksum()
3926 return 0; in rtl8152_check_firmware()
3948 for (i = 0; i < num; i++) in rtl8152_fw_phy_nc_apply()
3956 for (i = 0; i < num; i++) { in rtl8152_fw_phy_nc_apply()
4001 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data, in rtl8152_fw_mac_apply()
4009 for (i = 0; i < bp_num; i++) { in rtl8152_fw_mac_apply()
4033 u16 key_addr = 0; in rtl8152_apply_firmware()
4100 rc = 0; in rtl8152_request_firmware()
4105 if (rc < 0) in rtl8152_request_firmware()
4109 if (rc < 0) in rtl8152_request_firmware()
4149 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); in r8152_mmd_read()
4158 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); in r8152_mmd_write()
4226 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); in rtl_eee_enable()
4240 ocp_reg_write(tp, OCP_EEE_ADV, 0); in rtl_eee_enable()
4281 for (i = 0; i < 1000; i++) { in wait_oob_link_list_ready()
4300 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); in r8152b_exit_oob()
4401 for (i = 0; i < 104; i++) { in r8153_pre_firmware_1()
4409 return 0; in r8153_pre_firmware_1()
4421 return 0; in r8153_post_firmware_1()
4434 return 0; in r8153_pre_firmware_2()
4444 ocp_data |= BIT(0); in r8153_post_firmware_2()
4462 return 0; in r8153_post_firmware_2()
4477 return 0; in r8153_post_firmware_3()
4486 return 0; in r8153b_pre_firmware_1()
4497 ocp_data |= BIT(0); in r8153b_post_firmware_1()
4513 return 0; in r8153b_post_firmware_1()
4529 for (i = 0; i < 20; i++) { in r8153_aldps_en()
4531 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) in r8153_aldps_en()
4568 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); in r8153_hw_phy_cfg()
4575 sram_write(tp, SRAM_LPF_CFG, 0xf70f); in r8153_hw_phy_cfg()
4578 sram_write(tp, SRAM_10M_AMP1, 0x00af); in r8153_hw_phy_cfg()
4579 sram_write(tp, SRAM_10M_AMP2, 0x0208); in r8153_hw_phy_cfg()
4636 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake in r8153b_hw_phy_cfg()
4640 ocp_data = r8152_efuse_read(tp, 0x7d); in r8153b_hw_phy_cfg()
4641 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); in r8153b_hw_phy_cfg()
4642 if (data != 0xffff) in r8153b_hw_phy_cfg()
4646 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] in r8153b_hw_phy_cfg()
4649 ocp_data = ocp_reg_read(tp, 0xc426); in r8153b_hw_phy_cfg()
4650 ocp_data &= 0x3fff; in r8153b_hw_phy_cfg()
4678 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); in r8153b_hw_phy_cfg()
4782 * type. Set it to zero. bits[7:0] are the W1C bits about in r8153_enter_oob()
4785 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); in r8153_enter_oob()
4821 int ret = 0; in rtl8152_set_speed()
4861 tp->mii.full_duplex = 0; in rtl8152_set_speed()
4921 tp->mii.force_media = 0; in rtl8152_set_speed()
4932 for (i = 0; i < 50; i++) { in rtl8152_set_speed()
4934 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) in rtl8152_set_speed()
5076 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); in rtl8152_in_nway()
5077 tp->ocp_base = 0x2000; in rtl8152_in_nway()
5078 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ in rtl8152_in_nway()
5079 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); in rtl8152_in_nway()
5082 if (nway_state & 0xc000) in rtl8152_in_nway()
5090 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; in rtl8153_in_nway()
5145 if (usb_autopm_get_interface(tp->intf) < 0) in rtl_work_func_t()
5152 schedule_delayed_work(&tp->schedule, 0); in rtl_work_func_t()
5180 if (usb_autopm_get_interface(tp->intf) < 0) in rtl_hw_phy_work_func_t()
5236 int res = 0; in rtl8152_open()
5248 if (res < 0) in rtl8152_open()
5277 return 0; in rtl8152_open()
5291 int res = 0; in rtl8152_close()
5304 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { in rtl8152_close()
5385 for (i = 0; i < 500; i++) { in r8153_init()
5395 data = r8153_phy_status(tp, 0); in r8153_init()
5426 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) in r8153_init()
5433 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) in r8153_init()
5474 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); in r8153_init()
5525 for (i = 0; i < 500; i++) { in r8153b_init()
5535 data = r8153_phy_status(tp, 0); in r8153b_init()
5547 /* MSC timer = 0xfff * 8ms = 32760 ms */ in r8153b_init()
5548 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); in r8153b_init()
5581 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) { in r8153b_init()
5606 return 0; in rtl8152_pre_reset()
5610 return 0; in rtl8152_pre_reset()
5624 return 0; in rtl8152_pre_reset()
5634 return 0; in rtl8152_post_reset()
5637 if (determine_ethernet_addr(tp, &sa) >= 0) { in rtl8152_post_reset()
5645 return 0; in rtl8152_post_reset()
5664 return 0; in rtl8152_post_reset()
5726 return 0; in rtl8152_runtime_resume()
5742 return 0; in rtl8152_system_resume()
5748 int ret = 0; in rtl8152_runtime_suspend()
5754 u32 rcr = 0; in rtl8152_runtime_suspend()
5819 return 0; in rtl8152_system_suspend()
5862 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); in rtl8152_reset_resume()
5871 if (usb_autopm_get_interface(tp->intf) < 0) in rtl8152_get_wol()
5875 wol->supported = 0; in rtl8152_get_wol()
5876 wol->wolopts = 0; in rtl8152_get_wol()
5899 if (ret < 0) in rtl8152_set_wol()
5953 if (ret < 0) in rtl8152_get_link_ksettings()
5972 u32 advertising = 0; in rtl8152_set_link_ksettings()
5976 if (ret < 0) in rtl8152_set_link_ksettings()
6054 if (usb_autopm_get_interface(tp->intf) < 0) in rtl8152_get_ethtool_stats()
6061 data[0] = le64_to_cpu(tally.tx_packets); in rtl8152_get_ethtool_stats()
6087 u32 lp, adv, supported = 0; in r8152_get_eee()
6105 return 0; in r8152_get_eee()
6117 return 0; in r8152_set_eee()
6122 u32 lp, adv, supported = 0; in r8153_get_eee()
6140 return 0; in r8153_get_eee()
6150 if (ret < 0) in rtl_ethtool_get_eee()
6172 if (ret < 0) in rtl_ethtool_set_eee()
6195 if (ret < 0) in rtl8152_nway_reset()
6226 return 0; in rtl8152_get_coalesce()
6248 if (ret < 0) in rtl8152_set_coalesce()
6289 return 0; in rtl8152_get_tunable()
6324 return 0; in rtl8152_set_tunable()
6356 return 0; in rtl8152_set_ringparam()
6393 if (res < 0) in rtl8152_ioctl()
6437 return 0; in rtl8152_change_mtu()
6443 if (ret < 0) in rtl8152_change_mtu()
6508 int ret = 0; in rtl_ops_init()
6615 return 0; in rtl_fw_init()
6621 u32 ocp_data = 0; in rtl_get_version()
6628 return 0; in rtl_get_version()
6630 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), in rtl_get_version()
6633 if (ret > 0) in rtl_get_version()
6639 case 0x4c00: in rtl_get_version()
6642 case 0x4c10: in rtl_get_version()
6645 case 0x5c00: in rtl_get_version()
6648 case 0x5c10: in rtl_get_version()
6651 case 0x5c20: in rtl_get_version()
6654 case 0x5c30: in rtl_get_version()
6657 case 0x4800: in rtl_get_version()
6660 case 0x6000: in rtl_get_version()
6663 case 0x6010: in rtl_get_version()
6668 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); in rtl_get_version()
6672 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); in rtl_get_version()
6706 tp->msg_enable = 0x7FFF; in rtl8152_probe()
6717 tp->mii.supports_gmii = 0; in rtl8152_probe()
6764 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && in rtl8152_probe()
6789 tp->mii.phy_id_mask = 0x3f; in rtl8152_probe()
6790 tp->mii.reg_num_mask = 0x1f; in rtl8152_probe()
6809 __rtl_set_wol(tp, 0); in rtl8152_probe()
6818 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); in rtl8152_probe()
6825 if (ret != 0) { in rtl8152_probe()
6837 return 0; in rtl8152_probe()
6882 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
6883 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
6884 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
6885 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
6886 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
6887 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
6888 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
6889 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
6890 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
6891 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
6892 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082)},
6893 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
6894 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
6895 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
6896 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387)},
6897 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
6898 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
6899 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},