69 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
78 		phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);  in asix_get_phyid()
91 	phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);  in asix_get_phyid()
104 	return mii_link_ok(&dev->mii);  in asix_get_link()
111 	return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);  in asix_ioctl()
176 	mii_check_media(&dev->mii, 1, 1);  in ax88172_link_reset()
177 	mii_ethtool_gset(&dev->mii, &ecmd);  in ax88172_link_reset()
208 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits);  in asix_phy_reset()
215 		if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR)  in asix_phy_reset()
223 		   dev->mii.phy_id);  in asix_phy_reset()
259 	/* Initialize MII structure */  in ax88172_bind()
260 	dev->mii.dev = dev->net;  in ax88172_bind()
261 	dev->mii.mdio_read = asix_mdio_read;  in ax88172_bind()
262 	dev->mii.mdio_write = asix_mdio_write;  in ax88172_bind()
263 	dev->mii.phy_id_mask = 0x3f;  in ax88172_bind()
264 	dev->mii.reg_num_mask = 0x1f;  in ax88172_bind()
265 	dev->mii.phy_id = asix_get_phy_addr(dev);  in ax88172_bind()
273 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,  in ax88172_bind()
275 	mii_nway_restart(&dev->mii);  in ax88172_bind()
303 	mii_check_media(&dev->mii, 1, 1);  in ax88772_link_reset()
304 	mii_ethtool_gset(&dev->mii, &ecmd);  in ax88772_link_reset()
359 	embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);  in ax88772_hw_reset()
394 	if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,  in ax88772_hw_reset()
454 	embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);  in ax88772a_hw_reset()
486 	if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
507 		phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
509 		phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
511 		phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
520 			asix_mdio_write_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
524 			asix_mdio_write_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
528 			asix_mdio_write_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
605 		asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_BMCR);  in ax88772_suspend()
609 		asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE);  in ax88772_suspend()
629 		asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE,  in ax88772_restore_phy()
636 		asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_BMCR,  in ax88772_restore_phy()
714 	/* Initialize MII structure */  in ax88772_bind()
715 	dev->mii.dev = dev->net;  in ax88772_bind()
716 	dev->mii.mdio_read = asix_mdio_read;  in ax88772_bind()
717 	dev->mii.mdio_write = asix_mdio_write;  in ax88772_bind()
718 	dev->mii.phy_id_mask = 0x1f;  in ax88772_bind()
719 	dev->mii.reg_num_mask = 0x1f;  in ax88772_bind()
720 	dev->mii.phy_id = asix_get_phy_addr(dev);  in ax88772_bind()
796 	reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);  in marvell_phy_init()
799 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,  in marvell_phy_init()
803 		reg = asix_mdio_read(dev->net, dev->mii.phy_id,  in marvell_phy_init()
809 		asix_mdio_write(dev->net, dev->mii.phy_id,  in marvell_phy_init()
812 		reg = asix_mdio_read(dev->net, dev->mii.phy_id,  in marvell_phy_init()
827 	asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);  in rtl8211cl_phy_init()
828 	asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);  in rtl8211cl_phy_init()
829 	asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,  in rtl8211cl_phy_init()
830 		asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);  in rtl8211cl_phy_init()
831 	asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);  in rtl8211cl_phy_init()
834 		asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);  in rtl8211cl_phy_init()
835 		asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);  in rtl8211cl_phy_init()
836 		asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);  in rtl8211cl_phy_init()
844 	u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);  in marvell_led_status()
863 	asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);  in marvell_led_status()
914 	/* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */  in ax88178_reset()
932 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,  in ax88178_reset()
934 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,  in ax88178_reset()
938 	mii_nway_restart(&dev->mii);  in ax88178_reset()
963 	mii_check_media(&dev->mii, 1, 1);  in ax88178_link_reset()
964 	mii_ethtool_gset(&dev->mii, &ecmd);  in ax88178_link_reset()
1077 	/* Initialize MII structure */  in ax88178_bind()
1078 	dev->mii.dev = dev->net;  in ax88178_bind()
1079 	dev->mii.mdio_read = asix_mdio_read;  in ax88178_bind()
1080 	dev->mii.mdio_write = asix_mdio_write;  in ax88178_bind()
1081 	dev->mii.phy_id_mask = 0x1f;  in ax88178_bind()
1082 	dev->mii.reg_num_mask = 0xff;  in ax88178_bind()
1083 	dev->mii.supports_gmii = 1;  in ax88178_bind()
1084 	dev->mii.phy_id = asix_get_phy_addr(dev);  in ax88178_bind()