15 #define MII_VSC82X4_EXT_PAGE_16E	0x10
16 #define MII_VSC82X4_EXT_PAGE_17E	0x11
17 #define MII_VSC82X4_EXT_PAGE_18E	0x12
20 #define MII_VSC8244_EXT_CON1           0x17
21 #define MII_VSC8244_EXTCON1_INIT       0x0000
22 #define MII_VSC8244_EXTCON1_TX_SKEW_MASK	0x0c00
23 #define MII_VSC8244_EXTCON1_RX_SKEW_MASK	0x0300
24 #define MII_VSC8244_EXTCON1_TX_SKEW	0x0800
25 #define MII_VSC8244_EXTCON1_RX_SKEW	0x0200
28 #define MII_VSC8244_IMASK		0x19
29 #define MII_VSC8244_IMASK_IEN		0x8000
30 #define MII_VSC8244_IMASK_SPEED		0x4000
31 #define MII_VSC8244_IMASK_LINK		0x2000
32 #define MII_VSC8244_IMASK_DUPLEX	0x1000
33 #define MII_VSC8244_IMASK_MASK		0xf000
35 #define MII_VSC8221_IMASK_MASK		0xa000
38 #define MII_VSC8244_ISTAT		0x1a
39 #define MII_VSC8244_ISTAT_STATUS	0x8000
40 #define MII_VSC8244_ISTAT_SPEED		0x4000
41 #define MII_VSC8244_ISTAT_LINK		0x2000
42 #define MII_VSC8244_ISTAT_DUPLEX	0x1000
45 #define MII_VSC8244_AUX_CONSTAT		0x1c
46 #define MII_VSC8244_AUXCONSTAT_INIT	0x0000
47 #define MII_VSC8244_AUXCONSTAT_DUPLEX	0x0020
48 #define MII_VSC8244_AUXCONSTAT_SPEED	0x0018
49 #define MII_VSC8244_AUXCONSTAT_GBIT	0x0010
50 #define MII_VSC8244_AUXCONSTAT_100	0x0008
52 #define MII_VSC8221_AUXCONSTAT_INIT	0x0004 /* need to set this bit? */
53 #define MII_VSC8221_AUXCONSTAT_RESERVED	0x0004
56 #define MII_VSC82X4_EXT_PAGE_ACCESS	0x1f
59 #define MII_VSC8601_EPHY_CTL		0x17
62 #define PHY_ID_VSC8234			0x000fc620
63 #define PHY_ID_VSC8244			0x000fc6c0
64 #define PHY_ID_VSC8572			0x000704d0
65 #define PHY_ID_VSC8601			0x00070420
66 #define PHY_ID_VSC7385			0x00070450
67 #define PHY_ID_VSC7388			0x00070480
68 #define PHY_ID_VSC7395			0x00070550
69 #define PHY_ID_VSC7398			0x00070580
70 #define PHY_ID_VSC8662			0x00070660
71 #define PHY_ID_VSC8221			0x000fc550
72 #define PHY_ID_VSC8211			0x000fc4b0
85 	if (extcon < 0)  in vsc824x_add_skew()
105 	if (err < 0)  in vsc824x_config_init()
114 #define VSC73XX_EXT_PAGE_ACCESS 0x1f
129 	phy_write(phydev, 0x1f, 0x2a30);  in vsc73xx_config_init()
130 	phy_modify(phydev, 0x0c, 0x0300, 0x0200);  in vsc73xx_config_init()
131 	phy_write(phydev, 0x1f, 0x0000);  in vsc73xx_config_init()
133 	/* Config LEDs 0x61 */  in vsc73xx_config_init()
134 	phy_modify(phydev, MII_TPISTATUS, 0xff00, 0x0061);  in vsc73xx_config_init()
145 	phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
146 	phy_modify(phydev, 0x08, 0x0200, 0x0200);  in vsc738x_config_init()
147 	phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
148 	phy_write(phydev, 0x10, 0xb68a);  in vsc738x_config_init()
149 	phy_modify(phydev, 0x12, 0xff07, 0x0003);  in vsc738x_config_init()
150 	phy_modify(phydev, 0x11, 0x00ff, 0x00a2);  in vsc738x_config_init()
151 	phy_write(phydev, 0x10, 0x968a);  in vsc738x_config_init()
152 	phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
153 	phy_modify(phydev, 0x08, 0x0200, 0x0000);  in vsc738x_config_init()
154 	phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
158 	rev &= 0x0f;  in vsc738x_config_init()
160 	/* Special quirk for revision 0 */  in vsc738x_config_init()
161 	if (rev == 0) {  in vsc738x_config_init()
162 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
163 		phy_modify(phydev, 0x08, 0x0200, 0x0200);  in vsc738x_config_init()
164 		phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
165 		phy_write(phydev, 0x12, 0x0000);  in vsc738x_config_init()
166 		phy_write(phydev, 0x11, 0x0689);  in vsc738x_config_init()
167 		phy_write(phydev, 0x10, 0x8f92);  in vsc738x_config_init()
168 		phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
169 		phy_write(phydev, 0x12, 0x0000);  in vsc738x_config_init()
170 		phy_write(phydev, 0x11, 0x0e35);  in vsc738x_config_init()
171 		phy_write(phydev, 0x10, 0x9786);  in vsc738x_config_init()
172 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
173 		phy_modify(phydev, 0x08, 0x0200, 0x0000);  in vsc738x_config_init()
174 		phy_write(phydev, 0x17, 0xff80);  in vsc738x_config_init()
175 		phy_write(phydev, 0x17, 0x0000);  in vsc738x_config_init()
178 	phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
179 	phy_write(phydev, 0x12, 0x0048);  in vsc738x_config_init()
181 	if (rev == 0) {  in vsc738x_config_init()
182 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
183 		phy_write(phydev, 0x14, 0x6600);  in vsc738x_config_init()
184 		phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
185 		phy_write(phydev, 0x18, 0xa24e);  in vsc738x_config_init()
187 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
188 		phy_modify(phydev, 0x16, 0x0fc0, 0x0240);  in vsc738x_config_init()
189 		phy_modify(phydev, 0x14, 0x6000, 0x4000);  in vsc738x_config_init()
190 		/* bits 14-15 in extended register 0x14 controls DACG amplitude  in vsc738x_config_init()
193 		phy_write(phydev, 0x1f, 0x0001);  in vsc738x_config_init()
194 		phy_modify(phydev, 0x14, 0xe000, 0x6000);  in vsc738x_config_init()
195 		phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
200 	return 0;  in vsc738x_config_init()
210 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
211 	phy_modify(phydev, 0x08, 0x0200, 0x0200);  in vsc739x_config_init()
212 	phy_write(phydev, 0x1f, 0x52b5);  in vsc739x_config_init()
213 	phy_write(phydev, 0x10, 0xb68a);  in vsc739x_config_init()
214 	phy_modify(phydev, 0x12, 0xff07, 0x0003);  in vsc739x_config_init()
215 	phy_modify(phydev, 0x11, 0x00ff, 0x00a2);  in vsc739x_config_init()
216 	phy_write(phydev, 0x10, 0x968a);  in vsc739x_config_init()
217 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
218 	phy_modify(phydev, 0x08, 0x0200, 0x0000);  in vsc739x_config_init()
219 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
221 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
222 	phy_write(phydev, 0x12, 0x0048);  in vsc739x_config_init()
223 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
224 	phy_modify(phydev, 0x16, 0x0fc0, 0x0240);  in vsc739x_config_init()
225 	phy_modify(phydev, 0x14, 0x6000, 0x4000);  in vsc739x_config_init()
226 	phy_write(phydev, 0x1f, 0x0001);  in vsc739x_config_init()
227 	phy_modify(phydev, 0x14, 0xe000, 0x6000);  in vsc739x_config_init()
228 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
232 	return 0;  in vsc739x_config_init()
242 	return 0;  in vsc73xx_config_aneg()
253 	if (ret < 0)  in vsc8601_add_skew()
262 	int ret = 0;  in vsc8601_config_init()
267 	if (ret < 0)  in vsc8601_config_init()
270 	return 0;  in vsc8601_config_init()
275 	int err = 0;  in vsc824x_ack_interrupt()
284 	return (err < 0) ? err : 0;  in vsc824x_ack_interrupt()
305 		if (err < 0)  in vsc82xx_config_intr()
308 		err = phy_write(phydev, MII_VSC8244_IMASK, 0);  in vsc82xx_config_intr()
338 		return 0;  in vsc82x4_config_autocross_enable()
340 	/* map extended registers set 0x10 - 0x1e */  in vsc82x4_config_autocross_enable()
341 	ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5);  in vsc82x4_config_autocross_enable()
342 	if (ret >= 0)  in vsc82x4_config_autocross_enable()
343 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012);  in vsc82x4_config_autocross_enable()
344 	if (ret >= 0)  in vsc82x4_config_autocross_enable()
345 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803);  in vsc82x4_config_autocross_enable()
346 	if (ret >= 0)  in vsc82x4_config_autocross_enable()
347 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa);  in vsc82x4_config_autocross_enable()
348 	/* map standard registers set 0x10 - 0x1e */  in vsc82x4_config_autocross_enable()
349 	if (ret >= 0)  in vsc82x4_config_autocross_enable()
350 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);  in vsc82x4_config_autocross_enable()
352 		phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);  in vsc82x4_config_autocross_enable()
375 		if (ret < 0) /* error */  in vsc82x4_config_aneg()
389 	.phy_id_mask    = 0x000ffff0,
398 	.phy_id_mask	= 0x000fffc0,
407 	.phy_id_mask    = 0x000ffff0,
416 	.phy_id_mask    = 0x000ffff0,
424 	.phy_id_mask    = 0x000ffff0,
433 	.phy_id_mask    = 0x000ffff0,
442 	.phy_id_mask    = 0x000ffff0,
451 	.phy_id_mask    = 0x000ffff0,
460 	.phy_id_mask    = 0x000ffff0,
469 	.phy_id_mask	= 0x000ffff0,
478 	.phy_id_mask	= 0x000ffff0,
489 	{ PHY_ID_VSC8234, 0x000ffff0 },
490 	{ PHY_ID_VSC8244, 0x000fffc0 },
491 	{ PHY_ID_VSC8572, 0x000ffff0 },
492 	{ PHY_ID_VSC7385, 0x000ffff0 },
493 	{ PHY_ID_VSC7388, 0x000ffff0 },
494 	{ PHY_ID_VSC7395, 0x000ffff0 },
495 	{ PHY_ID_VSC7398, 0x000ffff0 },
496 	{ PHY_ID_VSC8662, 0x000ffff0 },
497 	{ PHY_ID_VSC8221, 0x000ffff0 },
498 	{ PHY_ID_VSC8211, 0x000ffff0 },