692 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)  in phy_base_write()  function
716 	phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);  in vsc8584_csr_write()
717 	phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));  in vsc8584_csr_write()
718 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));  in vsc8584_csr_write()
727 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_cmd()
730 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);  in vsc8584_cmd()
739 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_cmd()
756 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_micro_deassert_reset()
768 		phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);  in vsc8584_micro_deassert_reset()
774 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);  in vsc8584_micro_deassert_reset()
776 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);  in vsc8584_micro_deassert_reset()
778 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_micro_deassert_reset()
793 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_micro_assert_reset()
798 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);  in vsc8584_micro_assert_reset()
800 	phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);  in vsc8584_micro_assert_reset()
801 	phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);  in vsc8584_micro_assert_reset()
805 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);  in vsc8584_micro_assert_reset()
807 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);  in vsc8584_micro_assert_reset()
811 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);  in vsc8584_micro_assert_reset()
813 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |  in vsc8584_micro_assert_reset()
819 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);  in vsc8584_micro_assert_reset()
821 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_micro_assert_reset()
832 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);  in vsc8584_get_fw_crc()
834 	phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);  in vsc8584_get_fw_crc()
835 	phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);  in vsc8584_get_fw_crc()
842 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);  in vsc8584_get_fw_crc()
847 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_get_fw_crc()
865 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_patch_fw()
871 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |  in vsc8584_patch_fw()
874 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |  in vsc8584_patch_fw()
876 	phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);  in vsc8584_patch_fw()
879 		phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |  in vsc8584_patch_fw()
883 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);  in vsc8584_patch_fw()
885 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_patch_fw()
896 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8574_is_serdes_init()
926 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8574_is_serdes_init()
1005 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8574_config_pre_init()
1010 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8574_config_pre_init()
1012 	phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);  in vsc8574_config_pre_init()
1019 	phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);  in vsc8574_config_pre_init()
1021 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8574_config_pre_init()
1023 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);  in vsc8574_config_pre_init()
1024 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);  in vsc8574_config_pre_init()
1025 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);  in vsc8574_config_pre_init()
1026 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);  in vsc8574_config_pre_init()
1030 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8574_config_pre_init()
1032 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8574_config_pre_init()
1037 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);  in vsc8574_config_pre_init()
1039 	phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);  in vsc8574_config_pre_init()
1041 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8574_config_pre_init()
1046 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8574_config_pre_init()
1050 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8574_config_pre_init()
1052 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8574_config_pre_init()
1057 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8574_config_pre_init()
1096 		phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8574_config_pre_init()
1099 		phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);  in vsc8574_config_pre_init()
1100 		phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);  in vsc8574_config_pre_init()
1101 		phy_base_write(phydev, MSCC_INT_MEM_CNTL,  in vsc8574_config_pre_init()
1120 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8574_config_pre_init()
1127 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8574_config_pre_init()
1172 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_config_pre_init()
1177 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8584_config_pre_init()
1179 	phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);  in vsc8584_config_pre_init()
1183 	phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);  in vsc8584_config_pre_init()
1190 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);  in vsc8584_config_pre_init()
1192 	phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);  in vsc8584_config_pre_init()
1194 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8584_config_pre_init()
1196 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);  in vsc8584_config_pre_init()
1200 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8584_config_pre_init()
1202 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8584_config_pre_init()
1204 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));  in vsc8584_config_pre_init()
1209 	phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);  in vsc8584_config_pre_init()
1211 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));  in vsc8584_config_pre_init()
1216 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);  in vsc8584_config_pre_init()
1218 	phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);  in vsc8584_config_pre_init()
1220 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8584_config_pre_init()
1225 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8584_config_pre_init()
1229 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8584_config_pre_init()
1231 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_config_pre_init()
1236 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8584_config_pre_init()
1279 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_config_pre_init()
1378 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_config_init()
1396 	ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);  in vsc8584_config_init()
1400 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_config_init()
1585 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8514_config_pre_init()
1590 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8514_config_pre_init()
1592 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8514_config_pre_init()
1596 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8514_config_pre_init()
1598 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8514_config_pre_init()
1603 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8514_config_pre_init()
1607 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8514_config_pre_init()
1609 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8514_config_pre_init()
1613 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8514_config_pre_init()
1624 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);  in vsc85xx_csr_ctrl_phy_read()
1634 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,  in vsc85xx_csr_ctrl_phy_read()
1638 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,  in vsc85xx_csr_ctrl_phy_read()
1660 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc85xx_csr_ctrl_phy_read()
1671 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);  in vsc85xx_csr_ctrl_phy_write()
1681 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,  in vsc85xx_csr_ctrl_phy_write()
1685 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val);  in vsc85xx_csr_ctrl_phy_write()
1688 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16));  in vsc85xx_csr_ctrl_phy_write()
1691 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,  in vsc85xx_csr_ctrl_phy_write()
1707 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc85xx_csr_ctrl_phy_write()
1779 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8514_config_init()
1788 	ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);  in vsc8514_config_init()
1792 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8514_config_init()