703 static int phy_base_read(struct phy_device *phydev, u32 regnum)  in phy_base_read()  function
734 		reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);  in vsc8584_cmd()
796 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8584_micro_assert_reset()
803 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8584_micro_assert_reset()
809 	reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);  in vsc8584_micro_assert_reset()
817 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8584_micro_assert_reset()
844 	*crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);  in vsc8584_get_fw_crc()
899 	reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));  in vsc8574_is_serdes_init()
905 	reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));  in vsc8574_is_serdes_init()
911 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8574_is_serdes_init()
917 	reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);  in vsc8574_is_serdes_init()
1008 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8574_config_pre_init()
1028 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8574_config_pre_init()
1048 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8574_config_pre_init()
1055 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8574_config_pre_init()
1175 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8584_config_pre_init()
1181 	reg = phy_base_read(phydev,  MSCC_PHY_BYPASS_CONTROL);  in vsc8584_config_pre_init()
1198 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8584_config_pre_init()
1206 	reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);  in vsc8584_config_pre_init()
1227 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8584_config_pre_init()
1234 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8584_config_pre_init()
1383 	val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);  in vsc8584_config_init()
1588 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8514_config_pre_init()
1594 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8514_config_pre_init()
1605 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8514_config_pre_init()
1611 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8514_config_pre_init()
1647 		val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);  in vsc85xx_csr_ctrl_phy_read()
1655 	val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17);  in vsc85xx_csr_ctrl_phy_read()
1658 	val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18);  in vsc85xx_csr_ctrl_phy_read()
1700 		val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);  in vsc85xx_csr_ctrl_phy_write()
1784 	val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);  in vsc8514_config_init()