Lines Matching +full:rx +full:- +full:tx +full:- +full:swap
1 // SPDX-License-Identifier: GPL-2.0
18 #include <dt-bindings/net/ti-dp83867.h>
183 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
190 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
195 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
196 mac = (u8 *)ndev->dev_addr; in dp83867_set_wol()
199 return -EINVAL; in dp83867_set_wol()
213 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol()
215 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83867_set_wol()
217 (wol->sopass[3] << 8) | wol->sopass[2]); in dp83867_set_wol()
219 (wol->sopass[5] << 8) | wol->sopass[4]); in dp83867_set_wol()
226 if (wol->wolopts & WAKE_UCAST) in dp83867_set_wol()
231 if (wol->wolopts & WAKE_BCAST) in dp83867_set_wol()
251 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | in dp83867_get_wol()
253 wol->wolopts = 0; in dp83867_get_wol()
258 wol->wolopts |= WAKE_UCAST; in dp83867_get_wol()
261 wol->wolopts |= WAKE_BCAST; in dp83867_get_wol()
264 wol->wolopts |= WAKE_MAGIC; in dp83867_get_wol()
269 wol->sopass[0] = (sopass_val & 0xff); in dp83867_get_wol()
270 wol->sopass[1] = (sopass_val >> 8); in dp83867_get_wol()
274 wol->sopass[2] = (sopass_val & 0xff); in dp83867_get_wol()
275 wol->sopass[3] = (sopass_val >> 8); in dp83867_get_wol()
279 wol->sopass[4] = (sopass_val & 0xff); in dp83867_get_wol()
280 wol->sopass[5] = (sopass_val >> 8); in dp83867_get_wol()
282 wol->wolopts |= WAKE_MAGICSECURE; in dp83867_get_wol()
286 wol->wolopts = 0; in dp83867_get_wol()
293 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in dp83867_config_intr()
326 phydev->duplex = DUPLEX_FULL; in dp83867_read_status()
328 phydev->duplex = DUPLEX_HALF; in dp83867_read_status()
331 phydev->speed = SPEED_1000; in dp83867_read_status()
333 phydev->speed = SPEED_100; in dp83867_read_status()
335 phydev->speed = SPEED_10; in dp83867_read_status()
365 return -EINVAL; in dp83867_get_downshift()
378 return -E2BIG; in dp83867_set_downshift()
400 return -EINVAL; in dp83867_set_downshift()
414 switch (tuna->id) { in dp83867_get_tunable()
418 return -EOPNOTSUPP; in dp83867_get_tunable()
425 switch (tuna->id) { in dp83867_set_tunable()
429 return -EOPNOTSUPP; in dp83867_set_tunable()
436 (struct dp83867_private *)phydev->priv; in dp83867_config_port_mirroring()
438 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) in dp83867_config_port_mirroring()
449 struct dp83867_private *dp83867 = phydev->priv; in dp83867_verify_rgmii_cfg()
454 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { in dp83867_verify_rgmii_cfg()
465 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n" in dp83867_verify_rgmii_cfg()
466 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n", in dp83867_verify_rgmii_cfg()
470 /* RX delay *must* be specified if internal delay of RX is used. */ in dp83867_verify_rgmii_cfg()
471 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in dp83867_verify_rgmii_cfg()
472 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && in dp83867_verify_rgmii_cfg()
473 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) { in dp83867_verify_rgmii_cfg()
474 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
475 return -EINVAL; in dp83867_verify_rgmii_cfg()
478 /* TX delay *must* be specified if internal delay of TX is used. */ in dp83867_verify_rgmii_cfg()
479 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in dp83867_verify_rgmii_cfg()
480 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && in dp83867_verify_rgmii_cfg()
481 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) { in dp83867_verify_rgmii_cfg()
482 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
483 return -EINVAL; in dp83867_verify_rgmii_cfg()
492 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init()
493 struct device *dev = &phydev->mdio.dev; in dp83867_of_init()
494 struct device_node *of_node = dev->of_node; in dp83867_of_init()
498 return -ENODEV; in dp83867_of_init()
501 ret = of_property_read_u32(of_node, "ti,clk-output-sel", in dp83867_of_init()
502 &dp83867->clk_output_sel); in dp83867_of_init()
505 dp83867->set_clk_output = true; in dp83867_of_init()
509 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && in dp83867_of_init()
510 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { in dp83867_of_init()
511 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", in dp83867_of_init()
512 dp83867->clk_output_sel); in dp83867_of_init()
513 return -EINVAL; in dp83867_of_init()
517 if (of_property_read_bool(of_node, "ti,max-output-impedance")) in dp83867_of_init()
518 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; in dp83867_of_init()
519 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) in dp83867_of_init()
520 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; in dp83867_of_init()
522 dp83867->io_impedance = -1; /* leave at default */ in dp83867_of_init()
524 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, in dp83867_of_init()
525 "ti,dp83867-rxctrl-strap-quirk"); in dp83867_of_init()
527 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, in dp83867_of_init()
528 "ti,sgmii-ref-clock-output-enable"); in dp83867_of_init()
530 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV; in dp83867_of_init()
531 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", in dp83867_of_init()
532 &dp83867->rx_id_delay); in dp83867_of_init()
533 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { in dp83867_of_init()
535 "ti,rx-internal-delay value of %u out of range\n", in dp83867_of_init()
536 dp83867->rx_id_delay); in dp83867_of_init()
537 return -EINVAL; in dp83867_of_init()
540 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV; in dp83867_of_init()
541 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", in dp83867_of_init()
542 &dp83867->tx_id_delay); in dp83867_of_init()
543 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { in dp83867_of_init()
545 "ti,tx-internal-delay value of %u out of range\n", in dp83867_of_init()
546 dp83867->tx_id_delay); in dp83867_of_init()
547 return -EINVAL; in dp83867_of_init()
550 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) in dp83867_of_init()
551 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; in dp83867_of_init()
553 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) in dp83867_of_init()
554 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; in dp83867_of_init()
556 ret = of_property_read_u32(of_node, "ti,fifo-depth", in dp83867_of_init()
557 &dp83867->tx_fifo_depth); in dp83867_of_init()
559 ret = of_property_read_u32(of_node, "tx-fifo-depth", in dp83867_of_init()
560 &dp83867->tx_fifo_depth); in dp83867_of_init()
562 dp83867->tx_fifo_depth = in dp83867_of_init()
566 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { in dp83867_of_init()
567 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", in dp83867_of_init()
568 dp83867->tx_fifo_depth); in dp83867_of_init()
569 return -EINVAL; in dp83867_of_init()
572 ret = of_property_read_u32(of_node, "rx-fifo-depth", in dp83867_of_init()
573 &dp83867->rx_fifo_depth); in dp83867_of_init()
575 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; in dp83867_of_init()
577 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { in dp83867_of_init()
578 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", in dp83867_of_init()
579 dp83867->rx_fifo_depth); in dp83867_of_init()
580 return -EINVAL; in dp83867_of_init()
596 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), in dp83867_probe()
599 return -ENOMEM; in dp83867_probe()
601 phydev->priv = dp83867; in dp83867_probe()
608 struct dp83867_private *dp83867 = phydev->priv; in dp83867_config_init()
623 if (dp83867->rxctrl_strap_quirk) in dp83867_config_init()
630 * be set to 0x2. This may causes the PHY link to be unstable - in dp83867_config_init()
642 phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
648 val |= (dp83867->tx_fifo_depth << in dp83867_config_init()
651 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
653 val |= (dp83867->rx_fifo_depth << in dp83867_config_init()
695 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in dp83867_config_init()
698 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) in dp83867_config_init()
701 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) in dp83867_config_init()
707 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV) in dp83867_config_init()
708 delay |= dp83867->rx_id_delay; in dp83867_config_init()
709 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV) in dp83867_config_init()
710 delay |= dp83867->tx_id_delay << in dp83867_config_init()
718 if (dp83867->io_impedance >= 0) in dp83867_config_init()
721 dp83867->io_impedance); in dp83867_config_init()
723 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
750 /* SGMII type is set to 4-wire mode by default. in dp83867_config_init()
752 * switch on 6-wire mode. in dp83867_config_init()
754 if (dp83867->sgmii_ref_clk_en) in dp83867_config_init()
769 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) in dp83867_config_init()
773 if (dp83867->set_clk_output) { in dp83867_config_init()
776 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { in dp83867_config_init()
780 val = dp83867->clk_output_sel << in dp83867_config_init()