Lines Matching +full:ts +full:- +full:attached
1 // SPDX-License-Identifier: GPL-2.0+
137 /* list of the other attached phyters, not chosen */
157 static int chosen_phy = -1;
186 index = gpio_tab[CALIBRATE_GPIO] - 1; in dp83640_gpio_defaults()
190 index = gpio_tab[PEROUT_GPIO] - 1; in dp83640_gpio_defaults()
195 index = gpio_tab[i] - 1; in dp83640_gpio_defaults()
197 pd[index].chan = i - EXTTS0_GPIO; in dp83640_gpio_defaults()
214 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val); in broadcast_write()
220 struct dp83640_private *dp83640 = phydev->priv; in ext_read()
223 if (dp83640->clock->page != page) { in ext_read()
225 dp83640->clock->page = page; in ext_read()
236 struct dp83640_private *dp83640 = phydev->priv; in ext_write()
238 if (dp83640->clock->page != page) { in ext_write()
240 dp83640->clock->page = page; in ext_write()
250 const struct timespec64 *ts, u16 cmd) in tdr_write() argument
252 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */ in tdr_write()
253 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */ in tdr_write()
254 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */ in tdr_write()
255 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/ in tdr_write()
268 sec = p->sec_lo; in phy2rxts()
269 sec |= p->sec_hi << 16; in phy2rxts()
271 rxts->ns = p->ns_lo; in phy2rxts()
272 rxts->ns |= (p->ns_hi & 0x3fff) << 16; in phy2rxts()
273 rxts->ns += ((u64)sec) * 1000000000ULL; in phy2rxts()
274 rxts->seqid = p->seqid; in phy2rxts()
275 rxts->msgtype = (p->msgtype >> 12) & 0xf; in phy2rxts()
276 rxts->hash = p->msgtype & 0x0fff; in phy2rxts()
277 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; in phy2rxts()
285 sec = p->sec_lo; in phy2txts()
286 sec |= p->sec_hi << 16; in phy2txts()
288 ns = p->ns_lo; in phy2txts()
289 ns |= (p->ns_hi & 0x3fff) << 16; in phy2txts()
299 struct dp83640_private *dp83640 = clock->chosen; in periodic_output()
300 struct phy_device *phydev = dp83640->phydev; in periodic_output()
305 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, in periodic_output()
308 return -EINVAL; in periodic_output()
323 mutex_lock(&clock->extreg_lock); in periodic_output()
326 mutex_unlock(&clock->extreg_lock); in periodic_output()
330 sec = clkreq->perout.start.sec; in periodic_output()
331 nsec = clkreq->perout.start.nsec; in periodic_output()
332 pwidth = clkreq->perout.period.sec * 1000000000UL; in periodic_output()
333 pwidth += clkreq->perout.period.nsec; in periodic_output()
336 mutex_lock(&clock->extreg_lock); in periodic_output()
360 mutex_unlock(&clock->extreg_lock); in periodic_output()
370 struct phy_device *phydev = clock->chosen->phydev; in ptp_dp83640_adjfine()
377 scaled_ppm = -scaled_ppm; in ptp_dp83640_adjfine()
389 mutex_lock(&clock->extreg_lock); in ptp_dp83640_adjfine()
394 mutex_unlock(&clock->extreg_lock); in ptp_dp83640_adjfine()
403 struct phy_device *phydev = clock->chosen->phydev; in ptp_dp83640_adjtime()
404 struct timespec64 ts; in ptp_dp83640_adjtime() local
409 ts = ns_to_timespec64(delta); in ptp_dp83640_adjtime()
411 mutex_lock(&clock->extreg_lock); in ptp_dp83640_adjtime()
413 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK); in ptp_dp83640_adjtime()
415 mutex_unlock(&clock->extreg_lock); in ptp_dp83640_adjtime()
421 struct timespec64 *ts) in ptp_dp83640_gettime() argument
425 struct phy_device *phydev = clock->chosen->phydev; in ptp_dp83640_gettime()
428 mutex_lock(&clock->extreg_lock); in ptp_dp83640_gettime()
437 mutex_unlock(&clock->extreg_lock); in ptp_dp83640_gettime()
439 ts->tv_nsec = val[0] | (val[1] << 16); in ptp_dp83640_gettime()
440 ts->tv_sec = val[2] | (val[3] << 16); in ptp_dp83640_gettime()
446 const struct timespec64 *ts) in ptp_dp83640_settime() argument
450 struct phy_device *phydev = clock->chosen->phydev; in ptp_dp83640_settime()
453 mutex_lock(&clock->extreg_lock); in ptp_dp83640_settime()
455 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK); in ptp_dp83640_settime()
457 mutex_unlock(&clock->extreg_lock); in ptp_dp83640_settime()
467 struct phy_device *phydev = clock->chosen->phydev; in ptp_dp83640_enable()
471 switch (rq->type) { in ptp_dp83640_enable()
474 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | in ptp_dp83640_enable()
478 return -EOPNOTSUPP; in ptp_dp83640_enable()
481 if ((rq->extts.flags & PTP_STRICT_FLAGS) && in ptp_dp83640_enable()
482 (rq->extts.flags & PTP_ENABLE_FEATURE) && in ptp_dp83640_enable()
483 (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES) in ptp_dp83640_enable()
484 return -EOPNOTSUPP; in ptp_dp83640_enable()
486 index = rq->extts.index; in ptp_dp83640_enable()
488 return -EINVAL; in ptp_dp83640_enable()
492 gpio_num = 1 + ptp_find_pin(clock->ptp_clock, in ptp_dp83640_enable()
495 return -EINVAL; in ptp_dp83640_enable()
497 if (rq->extts.flags & PTP_FALLING_EDGE) in ptp_dp83640_enable()
502 mutex_lock(&clock->extreg_lock); in ptp_dp83640_enable()
504 mutex_unlock(&clock->extreg_lock); in ptp_dp83640_enable()
509 if (rq->perout.flags) in ptp_dp83640_enable()
510 return -EOPNOTSUPP; in ptp_dp83640_enable()
511 if (rq->perout.index >= N_PER_OUT) in ptp_dp83640_enable()
512 return -EINVAL; in ptp_dp83640_enable()
513 return periodic_output(clock, rq, on, rq->perout.index); in ptp_dp83640_enable()
519 return -EOPNOTSUPP; in ptp_dp83640_enable()
528 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC && in ptp_dp83640_verify()
529 !list_empty(&clock->phylist)) in ptp_dp83640_verify()
543 struct dp83640_private *dp83640 = phydev->priv; in enable_status_frames()
544 struct dp83640_clock *clock = dp83640->clock; in enable_status_frames()
552 mutex_lock(&clock->extreg_lock); in enable_status_frames()
557 mutex_unlock(&clock->extreg_lock); in enable_status_frames()
559 if (!phydev->attached_dev) { in enable_status_frames()
561 "expected to find an attached netdevice\n"); in enable_status_frames()
566 if (dev_mc_add(phydev->attached_dev, status_frame_dst)) in enable_status_frames()
569 if (dev_mc_del(phydev->attached_dev, status_frame_dst)) in enable_status_frames()
579 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src))) in is_status_frame()
587 return time_after(jiffies, rxts->tmo); in expired()
596 list_for_each_safe(this, next, &dp83640->rxts) { in prune_rx_ts()
599 list_del_init(&rxts->list); in prune_rx_ts()
600 list_add(&rxts->list, &dp83640->rxpool); in prune_rx_ts()
624 struct timespec64 ts; in recalibrate() local
627 struct phy_device *master = clock->chosen->phydev; in recalibrate()
631 cal_gpio = 1 + ptp_find_pin_unlocked(clock->ptp_clock, PTP_PF_PHYSYNC, 0); in recalibrate()
633 pr_err("PHY calibration pin not available - PHY is not calibrated."); in recalibrate()
637 mutex_lock(&clock->extreg_lock); in recalibrate()
642 list_for_each(this, &clock->phylist) { in recalibrate()
644 enable_broadcast(tmp->phydev, clock->page, 1); in recalibrate()
645 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); in recalibrate()
646 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0); in recalibrate()
647 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE); in recalibrate()
649 enable_broadcast(master, clock->page, 1); in recalibrate()
661 list_for_each(this, &clock->phylist) { in recalibrate()
663 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt); in recalibrate()
703 list_for_each(this, &clock->phylist) { in recalibrate()
705 val = ext_read(tmp->phydev, PAGE4, PTP_STS); in recalibrate()
706 phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val); in recalibrate()
707 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS); in recalibrate()
708 phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val); in recalibrate()
709 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); in recalibrate()
710 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); in recalibrate()
711 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); in recalibrate()
712 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); in recalibrate()
713 diff = now - (s64) phy2txts(&event_ts); in recalibrate()
714 phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n", in recalibrate()
717 ts = ns_to_timespec64(diff); in recalibrate()
718 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK); in recalibrate()
724 list_for_each(this, &clock->phylist) { in recalibrate()
726 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); in recalibrate()
730 mutex_unlock(&clock->extreg_lock); in recalibrate()
768 dp83640->edata.sec_hi = phy_txts->sec_hi; in decode_evnt()
771 dp83640->edata.sec_lo = phy_txts->sec_lo; in decode_evnt()
774 dp83640->edata.ns_hi = phy_txts->ns_hi; in decode_evnt()
777 dp83640->edata.ns_lo = phy_txts->ns_lo; in decode_evnt()
781 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT; in decode_evnt()
786 event.timestamp = phy2txts(&dp83640->edata); in decode_evnt()
789 event.timestamp -= 35; in decode_evnt()
794 ptp_clock_event(dp83640->clock->ptp_clock, &event); in decode_evnt()
810 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */ in match()
818 if (rxts->msgtype != (msgtype & 0xf)) in match()
821 seqid = be16_to_cpu(hdr->sequence_id); in match()
822 if (rxts->seqid != seqid) in match()
826 (unsigned char *)&hdr->source_port_identity) >> 20; in match()
827 if (rxts->hash != hash) in match()
842 overflow = (phy_rxts->ns_hi >> 14) & 0x3; in decode_rxts()
846 spin_lock_irqsave(&dp83640->rx_lock, flags); in decode_rxts()
850 if (list_empty(&dp83640->rxpool)) { in decode_rxts()
854 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list); in decode_rxts()
855 list_del_init(&rxts->list); in decode_rxts()
858 spin_lock(&dp83640->rx_queue.lock); in decode_rxts()
859 skb_queue_walk(&dp83640->rx_queue, skb) { in decode_rxts()
862 skb_info = (struct dp83640_skb_info *)skb->cb; in decode_rxts()
863 if (match(skb, skb_info->ptp_type, rxts)) { in decode_rxts()
864 __skb_unlink(skb, &dp83640->rx_queue); in decode_rxts()
867 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); in decode_rxts()
868 list_add(&rxts->list, &dp83640->rxpool); in decode_rxts()
872 spin_unlock(&dp83640->rx_queue.lock); in decode_rxts()
875 list_add_tail(&rxts->list, &dp83640->rxts); in decode_rxts()
877 spin_unlock_irqrestore(&dp83640->rx_lock, flags); in decode_rxts()
894 skb = skb_dequeue(&dp83640->tx_queue); in decode_txts()
900 overflow = (phy_txts->ns_hi >> 14) & 0x3; in decode_txts()
905 skb = skb_dequeue(&dp83640->tx_queue); in decode_txts()
909 skb_info = (struct dp83640_skb_info *)skb->cb; in decode_txts()
910 if (time_after(jiffies, skb_info->tmo)) { in decode_txts()
930 ptr = skb->data + 2; in decode_status_frame()
932 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) { in decode_status_frame()
937 len -= sizeof(type); in decode_status_frame()
987 if (!list_empty(&clock->phylist)) { in dp83640_free_clocks()
988 pr_warn("phy list non-empty while unloading\n"); in dp83640_free_clocks()
991 list_del(&clock->list); in dp83640_free_clocks()
992 mutex_destroy(&clock->extreg_lock); in dp83640_free_clocks()
993 mutex_destroy(&clock->clock_lock); in dp83640_free_clocks()
994 put_device(&clock->bus->dev); in dp83640_free_clocks()
995 kfree(clock->caps.pin_config); in dp83640_free_clocks()
1004 INIT_LIST_HEAD(&clock->list); in dp83640_clock_init()
1005 clock->bus = bus; in dp83640_clock_init()
1006 mutex_init(&clock->extreg_lock); in dp83640_clock_init()
1007 mutex_init(&clock->clock_lock); in dp83640_clock_init()
1008 INIT_LIST_HEAD(&clock->phylist); in dp83640_clock_init()
1009 clock->caps.owner = THIS_MODULE; in dp83640_clock_init()
1010 sprintf(clock->caps.name, "dp83640 timer"); in dp83640_clock_init()
1011 clock->caps.max_adj = 1953124; in dp83640_clock_init()
1012 clock->caps.n_alarm = 0; in dp83640_clock_init()
1013 clock->caps.n_ext_ts = N_EXT_TS; in dp83640_clock_init()
1014 clock->caps.n_per_out = N_PER_OUT; in dp83640_clock_init()
1015 clock->caps.n_pins = DP83640_N_PINS; in dp83640_clock_init()
1016 clock->caps.pps = 0; in dp83640_clock_init()
1017 clock->caps.adjfine = ptp_dp83640_adjfine; in dp83640_clock_init()
1018 clock->caps.adjtime = ptp_dp83640_adjtime; in dp83640_clock_init()
1019 clock->caps.gettime64 = ptp_dp83640_gettime; in dp83640_clock_init()
1020 clock->caps.settime64 = ptp_dp83640_settime; in dp83640_clock_init()
1021 clock->caps.enable = ptp_dp83640_enable; in dp83640_clock_init()
1022 clock->caps.verify = ptp_dp83640_verify; in dp83640_clock_init()
1026 dp83640_gpio_defaults(clock->caps.pin_config); in dp83640_clock_init()
1030 get_device(&bus->dev); in dp83640_clock_init()
1036 if (chosen_phy == -1 && !clock->chosen) in choose_this_phy()
1039 if (chosen_phy == phydev->mdio.addr) in choose_this_phy()
1048 mutex_lock(&clock->clock_lock); in dp83640_clock_get()
1065 if (tmp->bus == bus) { in dp83640_clock_get_bus()
1077 clock->caps.pin_config = kcalloc(DP83640_N_PINS, in dp83640_clock_get_bus()
1080 if (!clock->caps.pin_config) { in dp83640_clock_get_bus()
1086 list_add_tail(&clock->list, &phyter_clocks); in dp83640_clock_get_bus()
1095 mutex_unlock(&clock->clock_lock); in dp83640_clock_put()
1117 struct dp83640_private *dp83640 = phydev->priv; in dp83640_config_init()
1118 struct dp83640_clock *clock = dp83640->clock; in dp83640_config_init()
1120 if (clock->chosen && !list_empty(&clock->phylist)) in dp83640_config_init()
1123 mutex_lock(&clock->extreg_lock); in dp83640_config_init()
1124 enable_broadcast(phydev, clock->page, 1); in dp83640_config_init()
1125 mutex_unlock(&clock->extreg_lock); in dp83640_config_init()
1130 mutex_lock(&clock->extreg_lock); in dp83640_config_init()
1132 mutex_unlock(&clock->extreg_lock); in dp83640_config_init()
1153 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in dp83640_config_intr()
1203 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) in dp83640_hwtstamp()
1204 return -EFAULT; in dp83640_hwtstamp()
1207 return -EINVAL; in dp83640_hwtstamp()
1210 return -ERANGE; in dp83640_hwtstamp()
1212 dp83640->hwts_tx_en = cfg.tx_type; in dp83640_hwtstamp()
1216 dp83640->hwts_rx_en = 0; in dp83640_hwtstamp()
1217 dp83640->layer = 0; in dp83640_hwtstamp()
1218 dp83640->version = 0; in dp83640_hwtstamp()
1223 dp83640->hwts_rx_en = 1; in dp83640_hwtstamp()
1224 dp83640->layer = PTP_CLASS_L4; in dp83640_hwtstamp()
1225 dp83640->version = PTP_CLASS_V1; in dp83640_hwtstamp()
1231 dp83640->hwts_rx_en = 1; in dp83640_hwtstamp()
1232 dp83640->layer = PTP_CLASS_L4; in dp83640_hwtstamp()
1233 dp83640->version = PTP_CLASS_V2; in dp83640_hwtstamp()
1239 dp83640->hwts_rx_en = 1; in dp83640_hwtstamp()
1240 dp83640->layer = PTP_CLASS_L2; in dp83640_hwtstamp()
1241 dp83640->version = PTP_CLASS_V2; in dp83640_hwtstamp()
1247 dp83640->hwts_rx_en = 1; in dp83640_hwtstamp()
1248 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2; in dp83640_hwtstamp()
1249 dp83640->version = PTP_CLASS_V2; in dp83640_hwtstamp()
1253 return -ERANGE; in dp83640_hwtstamp()
1256 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; in dp83640_hwtstamp()
1257 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; in dp83640_hwtstamp()
1259 if (dp83640->layer & PTP_CLASS_L2) { in dp83640_hwtstamp()
1263 if (dp83640->layer & PTP_CLASS_L4) { in dp83640_hwtstamp()
1268 if (dp83640->hwts_tx_en) in dp83640_hwtstamp()
1271 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC) in dp83640_hwtstamp()
1274 if (dp83640->hwts_rx_en) in dp83640_hwtstamp()
1277 mutex_lock(&dp83640->clock->extreg_lock); in dp83640_hwtstamp()
1279 ext_write(0, dp83640->phydev, PAGE5, PTP_TXCFG0, txcfg0); in dp83640_hwtstamp()
1280 ext_write(0, dp83640->phydev, PAGE5, PTP_RXCFG0, rxcfg0); in dp83640_hwtstamp()
1282 mutex_unlock(&dp83640->clock->extreg_lock); in dp83640_hwtstamp()
1284 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; in dp83640_hwtstamp()
1294 while ((skb = skb_dequeue(&dp83640->rx_queue))) { in rx_timestamp_work()
1297 skb_info = (struct dp83640_skb_info *)skb->cb; in rx_timestamp_work()
1298 if (!time_after(jiffies, skb_info->tmo)) { in rx_timestamp_work()
1299 skb_queue_head(&dp83640->rx_queue, skb); in rx_timestamp_work()
1306 if (!skb_queue_empty(&dp83640->rx_queue)) in rx_timestamp_work()
1307 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); in rx_timestamp_work()
1315 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; in dp83640_rxtstamp()
1327 if (!dp83640->hwts_rx_en) in dp83640_rxtstamp()
1330 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0) in dp83640_rxtstamp()
1333 spin_lock_irqsave(&dp83640->rx_lock, flags); in dp83640_rxtstamp()
1335 list_for_each_safe(this, next, &dp83640->rxts) { in dp83640_rxtstamp()
1340 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); in dp83640_rxtstamp()
1341 list_del_init(&rxts->list); in dp83640_rxtstamp()
1342 list_add(&rxts->list, &dp83640->rxpool); in dp83640_rxtstamp()
1346 spin_unlock_irqrestore(&dp83640->rx_lock, flags); in dp83640_rxtstamp()
1349 skb_info->ptp_type = type; in dp83640_rxtstamp()
1350 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; in dp83640_rxtstamp()
1351 skb_queue_tail(&dp83640->rx_queue, skb); in dp83640_rxtstamp()
1352 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); in dp83640_rxtstamp()
1363 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; in dp83640_txtstamp()
1367 switch (dp83640->hwts_tx_en) { in dp83640_txtstamp()
1376 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; in dp83640_txtstamp()
1377 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; in dp83640_txtstamp()
1378 skb_queue_tail(&dp83640->tx_queue, skb); in dp83640_txtstamp()
1394 info->so_timestamping = in dp83640_ts_info()
1398 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock); in dp83640_ts_info()
1399 info->tx_types = in dp83640_ts_info()
1403 info->rx_filters = in dp83640_ts_info()
1416 int err = -ENOMEM, i; in dp83640_probe()
1418 if (phydev->mdio.addr == BROADCAST_ADDR) in dp83640_probe()
1421 clock = dp83640_clock_get_bus(phydev->mdio.bus); in dp83640_probe()
1429 dp83640->phydev = phydev; in dp83640_probe()
1430 dp83640->mii_ts.rxtstamp = dp83640_rxtstamp; in dp83640_probe()
1431 dp83640->mii_ts.txtstamp = dp83640_txtstamp; in dp83640_probe()
1432 dp83640->mii_ts.hwtstamp = dp83640_hwtstamp; in dp83640_probe()
1433 dp83640->mii_ts.ts_info = dp83640_ts_info; in dp83640_probe()
1435 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work); in dp83640_probe()
1436 INIT_LIST_HEAD(&dp83640->rxts); in dp83640_probe()
1437 INIT_LIST_HEAD(&dp83640->rxpool); in dp83640_probe()
1439 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool); in dp83640_probe()
1441 phydev->mii_ts = &dp83640->mii_ts; in dp83640_probe()
1442 phydev->priv = dp83640; in dp83640_probe()
1444 spin_lock_init(&dp83640->rx_lock); in dp83640_probe()
1445 skb_queue_head_init(&dp83640->rx_queue); in dp83640_probe()
1446 skb_queue_head_init(&dp83640->tx_queue); in dp83640_probe()
1448 dp83640->clock = clock; in dp83640_probe()
1451 clock->chosen = dp83640; in dp83640_probe()
1452 clock->ptp_clock = ptp_clock_register(&clock->caps, in dp83640_probe()
1453 &phydev->mdio.dev); in dp83640_probe()
1454 if (IS_ERR(clock->ptp_clock)) { in dp83640_probe()
1455 err = PTR_ERR(clock->ptp_clock); in dp83640_probe()
1459 list_add_tail(&dp83640->list, &clock->phylist); in dp83640_probe()
1465 clock->chosen = NULL; in dp83640_probe()
1477 struct dp83640_private *tmp, *dp83640 = phydev->priv; in dp83640_remove()
1479 if (phydev->mdio.addr == BROADCAST_ADDR) in dp83640_remove()
1482 phydev->mii_ts = NULL; in dp83640_remove()
1485 cancel_delayed_work_sync(&dp83640->ts_work); in dp83640_remove()
1487 skb_queue_purge(&dp83640->rx_queue); in dp83640_remove()
1488 skb_queue_purge(&dp83640->tx_queue); in dp83640_remove()
1490 clock = dp83640_clock_get(dp83640->clock); in dp83640_remove()
1492 if (dp83640 == clock->chosen) { in dp83640_remove()
1493 ptp_clock_unregister(clock->ptp_clock); in dp83640_remove()
1494 clock->chosen = NULL; in dp83640_remove()
1496 list_for_each_safe(this, next, &clock->phylist) { in dp83640_remove()
1499 list_del_init(&tmp->list); in dp83640_remove()