75 	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);  in bcm7xxx_28nm_d0_afe_config_init()
103 	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);  in bcm7xxx_28nm_e0_plus_afe_config_init()
231 	ret = phy_write(dev, location, v);  in phy_set_clr_bits()
249 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0);  in bcm7xxx_28nm_ephy_01_afe_config_init()
254 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_01_afe_config_init()
264 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_01_afe_config_init()
320 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_eee_enable()
324 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_eee_enable()
330 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_eee_enable()
334 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_eee_enable()
339 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_eee_enable()
343 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_eee_enable()
349 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_eee_enable()
353 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_eee_enable()
366 	phy_write(phydev, MII_BMCR,  in bcm7xxx_28nm_ephy_eee_enable()
418 	phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO);  in bcm7xxx_config_init()
428 	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);  in bcm7xxx_config_init()
432 	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);  in bcm7xxx_config_init()
434 	phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);  in bcm7xxx_config_init()
464 		ret = phy_write(phydev,  in bcm7xxx_suspend()