49 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);  in bcm7xxx_28nm_d0_afe_config_init()
52 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);  in bcm7xxx_28nm_d0_afe_config_init()
55 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);  in bcm7xxx_28nm_d0_afe_config_init()
58 	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);  in bcm7xxx_28nm_d0_afe_config_init()
61 	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);  in bcm7xxx_28nm_d0_afe_config_init()
64 	bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);  in bcm7xxx_28nm_d0_afe_config_init()
67 	bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);  in bcm7xxx_28nm_d0_afe_config_init()
72 	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);  in bcm7xxx_28nm_d0_afe_config_init()
78 	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);  in bcm7xxx_28nm_d0_afe_config_init()
89 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);  in bcm7xxx_28nm_e0_plus_afe_config_init()
92 	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);  in bcm7xxx_28nm_e0_plus_afe_config_init()
95 	bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);  in bcm7xxx_28nm_e0_plus_afe_config_init()
100 	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);  in bcm7xxx_28nm_e0_plus_afe_config_init()
106 	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);  in bcm7xxx_28nm_e0_plus_afe_config_init()
117 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);  in bcm7xxx_28nm_a0_patch_afe_config_init()
120 	bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);  in bcm7xxx_28nm_a0_patch_afe_config_init()
123 	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);  in bcm7xxx_28nm_a0_patch_afe_config_init()
126 	bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);  in bcm7xxx_28nm_a0_patch_afe_config_init()
129 	bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);  in bcm7xxx_28nm_a0_patch_afe_config_init()
132 	bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);  in bcm7xxx_28nm_a0_patch_afe_config_init()