Lines Matching +full:rx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
39 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
40 #define TxINT_ENAB 0x2 /* Tx Int Enable */
43 #define RxINT_DISAB 0 /* Rx Int Disable */
44 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
45 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
50 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
56 #define RxENABLE 0x1 /* Rx Enable */
59 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
62 #define Rx5 0x0 /* Rx 5 Bits/Character */
63 #define Rx7 0x40 /* Rx 7 Bits/Character */
64 #define Rx6 0x80 /* Rx 6 Bits/Character */
65 #define Rx8 0xc0 /* Rx 8 Bits/Character */
69 #define PAR_ENA 0x1 /* Parity Enable */
72 #define SYNC_ENAB 0 /* Sync Modes Enable */
89 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
91 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
92 #define TxENAB 0x8 /* Tx Enable */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
110 #define MIE 8 /* Master Interrupt Enable */
150 #define BRENABL 1 /* Baud rate generator enable */
173 #define Rx_CH_AV 0x1 /* Rx Character Available */
184 /* Residue Data for 8 Rx bits/char programmed */
193 /* Special Rx Condition Interrupts */
195 #define Rx_OVR 0x20 /* Rx Overrun Error */
199 /* Read Register 2 (channel b only) - Interrupt vector */
204 #define CHBRxIP 0x4 /* Channel B Rx IP */
207 #define CHARxIP 0x20 /* Channel A Rx IP */
230 #define RXFIFOH 0x08 /* Z85230: Int on RX FIFO half full */
237 #define SHDLCE 1 /* SDLC/HDLC Enhancements Enable */
238 #define FIFOE 4 /* FIFO Enable */