221 static void write_scc(struct scc_priv *priv, int reg, int val);
282 		write_scc(&info->priv[0], R9, FHWRES);  in dmascc_exit()
485 	write_scc(priv, R9, FHWRES | MIE | NV);  in setup_adapter()
488 	write_scc(priv, R15, SHDLCE);  in setup_adapter()
503 	write_scc(priv, R15, 0);  in setup_adapter()
516 		write_scc(priv, R15, CTSIE);  in setup_adapter()
517 		write_scc(priv, R0, RES_EXT_INT);  in setup_adapter()
518 		write_scc(priv, R1, EXT_INT_ENAB);  in setup_adapter()
534 		write_scc(priv, R1, 0);  in setup_adapter()
535 		write_scc(priv, R15, 0);  in setup_adapter()
536 		write_scc(priv, R0, RES_EXT_INT);  in setup_adapter()
602 	write_scc(&info->priv[0], R9, FHWRES);  in setup_adapter()
615 static void write_scc(struct scc_priv *priv, int reg, int val)  in write_scc()  function
749 	write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);  in scc_open()
751 	write_scc(priv, R4, SDLC | X1CLK);  in scc_open()
753 	write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);  in scc_open()
755 	write_scc(priv, R3, Rx8);  in scc_open()
757 	write_scc(priv, R5, Tx8);  in scc_open()
759 	write_scc(priv, R6, 0);  in scc_open()
761 	write_scc(priv, R7, FLAG);  in scc_open()
765 		write_scc(priv, R15, SHDLCE);  in scc_open()
767 		write_scc(priv, R7, AUTOEOM);  in scc_open()
768 		write_scc(priv, R15, 0);  in scc_open()
772 		write_scc(priv, R15, SHDLCE);  in scc_open()
794 				write_scc(priv, R7, AUTOEOM | TXFIFOE);  in scc_open()
796 				write_scc(priv, R7, AUTOEOM);  in scc_open()
798 			write_scc(priv, R7, AUTOEOM | RXFIFOH);  in scc_open()
800 		write_scc(priv, R15, 0);  in scc_open()
804 	write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ));  in scc_open()
809 		write_scc(priv, R12, priv->param.brg_tc & 0xFF);  in scc_open()
810 		write_scc(priv, R13, (priv->param.brg_tc >> 8) & 0xFF);  in scc_open()
813 		write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL);  in scc_open()
815 		write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL);  in scc_open()
818 		write_scc(priv, R14, DTRREQ | BRSRC);  in scc_open()
828 	write_scc(priv, R11, priv->param.clocks);  in scc_open()
847 	write_scc(priv, R15, DCDIE);  in scc_open()
871 	write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);  in scc_close()
946 		write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);  in scc_send_packet()
947 		write_scc(priv, R15, 0);  in scc_send_packet()
983 		write_scc(priv, R15, TxUIE);  in tx_on()
990 			write_scc(priv, R1,  in tx_on()
1001 		write_scc(priv, R15, TxUIE);  in tx_on()
1002 		write_scc(priv, R1,  in tx_on()
1008 		write_scc(priv, R0, RES_EOM_L);  in tx_on()
1036 		write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx |  in rx_on()
1042 		write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT |  in rx_on()
1045 	write_scc(priv, R0, ERR_RES);  in rx_on()
1046 	write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB);  in rx_on()
1053 	write_scc(priv, R3, Rx8);  in rx_off()
1058 		write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);  in rx_off()
1074 			write_scc(priv, R15, r15 | CTSIE);  in start_timer()
1106 		write_scc(&info->priv[0], R0, RES_H_IUS);  in z8530_isr()
1161 		write_scc(priv, R0, ERR_RES);  in rx_isr()
1193 			write_scc(priv, R0, ERR_RES);  in special_condition()
1292 		write_scc(priv, R0, RES_Tx_P);  in tx_isr()
1303 		write_scc(priv, R0, RES_EOM_L);  in tx_isr()
1316 	write_scc(priv, R0, RES_EXT_INT);  in es_isr()
1338 			write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);  in es_isr()
1344 			write_scc(priv, R0, RES_EXT_INT);  in es_isr()
1345 			write_scc(priv, R0, RES_EXT_INT);  in es_isr()
1357 		write_scc(priv, R15, 0);  in es_isr()
1375 				write_scc(priv, R15, 0);  in es_isr()
1383 				write_scc(priv, R15, 0);  in es_isr()
1405 		write_scc(priv, R5, TxCRC_ENAB | Tx8);  in tm_isr()
1408 			write_scc(priv, R15, 0);  in tm_isr()
1412 		write_scc(priv, R15, DCDIE);  in tm_isr()
1427 			write_scc(priv, R5,  in tm_isr()
1429 			write_scc(priv, R15, 0);  in tm_isr()
1434 				write_scc(priv, R15, DCDIE);  in tm_isr()
1439 		write_scc(priv, R15, DCDIE);  in tm_isr()