Lines Matching +full:rx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
33 /* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
36 /* VLAN Rx & Tx frame support. Default: disabled (cleared) */
39 /* Enable recognition of flow control frames on Rx. Default: enabled (set) */
52 /* Enable Length/Type error checking for incoming frames. When this option is
60 /* Enable the transmitter. Default: enabled (set) */
63 /* Enable the receiver. Default: enabled (set) */
122 /* Default TX/RX Threshold and waitbound values for SGDMA mode */
138 #define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */
139 #define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /* Last rx pkt */
147 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
150 #define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */
152 #define XAE_RTAG_OFFSET 0x0000001C /* Rx VLAN TAG */
158 #define XAE_RCW0_OFFSET 0x00000400 /* Rx Configuration Word 0 */
159 #define XAE_RCW1_OFFSET 0x00000404 /* Rx Configuration Word 1 */
176 #define XAE_RX_VLAN_DATA_OFFSET 0x00008000 /* RX VLAN data table address */
185 #define XAE_RAF_RXVTAGMODE_MASK 0x00000060 /* Rx VLAN TAG mode */
187 #define XAE_RAF_RXVSTRPMODE_MASK 0x00000600 /* Rx VLAN STRIP mode */
192 #define XAE_RAF_RXBADFRMEN_MASK 0x00004000 /* Recv Bad Frame Enable */
194 #define XAE_RAF_RXVTAGMODE_SHIFT 5 /* Rx Tag mode shift bits */
196 #define XAE_RAF_RXVSTRPMODE_SHIFT 9 /* Rx Strip mode shift bits*/
200 /* Transmit inter-frame gap adjustment value */
210 #define XAE_INT_RXCMPIT_MASK 0x00000004 /* Rx complete */
211 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
212 #define XAE_INT_RXFIFOOVR_MASK 0x00000010 /* Rx fifo overrun */
214 #define XAE_INT_RXDCMLOCK_MASK 0x00000040 /* Rx Dcm Lock */
233 #define XAE_RCW1_JUM_MASK 0x40000000 /* Jumbo frame enable */
234 /* In-Band FCS enable (FCS not stripped) */
236 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
237 #define XAE_RCW1_VLAN_MASK 0x08000000 /* VLAN frame enable */
249 #define XAE_TC_JUM_MASK 0x40000000 /* Jumbo frame enable */
250 /* In-Band FCS enable (FCS not generated) */
252 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
253 #define XAE_TC_VLAN_MASK 0x08000000 /* VLAN frame enable */
254 /* Inter-frame gap adjustment enable */
258 #define XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */
259 #define XAE_FCC_FCTX_MASK 0x40000000 /* Tx flow control enable */
263 #define XAE_EMMC_RGMII_MASK 0x20000000 /* RGMII mode enable */
264 #define XAE_EMMC_SGMII_MASK 0x10000000 /* SGMII mode enable */
265 #define XAE_EMMC_GPCS_MASK 0x08000000 /* 1000BaseX mode enable */
266 #define XAE_EMMC_HOST_MASK 0x04000000 /* Host interface enable */
267 #define XAE_EMMC_TX16BIT 0x02000000 /* 16 bit Tx client enable */
268 #define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */
276 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
286 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable */
311 #define XAE_FMI_PM_MASK 0x80000000 /* Promis. mode enable */
343 * struct axidma_bd - Axi Dma buffer descriptor layout
376 * struct axienet_local - axienet private per device data
386 * @rx_irq: Axidma RX IRQ number
387 * @phy_mode: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
393 * @rx_bd_v: Virtual address of the RX buffer descriptor ring
394 * @rx_bd_p: Physical address(start address) of the RX buffer descr. ring
400 * @rx_bd_ci: Stores the index of the Rx buffer descriptor in the ring being
406 * @rxmem: Stores rx memory size for jumbo frame handling.
408 * @csum_offload_on_rx_path: Stores the checksum selection on RX side.
409 * @coalesce_count_rx: Store the irq coalesce on RX side.
465 * struct axiethernet_option - Used to set axi ethernet hardware options
477 * axienet_ior - Memory mapped Axi Ethernet register read
487 return ioread32(lp->regs + offset); in axienet_ior()
496 * axienet_iow - Memory mapped Axi Ethernet register write
507 iowrite32(value, lp->regs + offset); in axienet_iow()