Lines Matching +full:poll +full:- +full:retry +full:- +full:count

1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE	0x0cUL		/* Local-memory Size		*/
45 /* The following registers are for per-qe channel information/status. */
59 #define CREG_PIPG	0x34UL	/* Inter-Frame Gap           */
74 #define CREG_STAT_CCOFLOW     0x00100000  /* TX Coll-counter Overflow  */
79 #define CREG_STAT_RCCOFLOW    0x00001000  /* RX Coll-counter Overflow  */
85 #define CREG_STAT_CECOFLOW    0x00000040  /* CRC Error-counter Overflow*/
115 #define CREG_MMASK_ERETRY     0x04000000  /* Excess retry              */
121 #define CREG_MMASK_RXCOLL     0x00000400  /* RX Coll-Cntr overflow     */
129 /* Per-channel AMD 79C940 MACE registers. */
134 #define MREGS_TXRCNT	0x04UL	/* Transmit Retry Count           */
137 #define MREGS_FFCNT	0x07UL	/* FIFO Frame Count               */
140 #define MREGS_POLL	0x0aUL	/* POLL Register                  */
146 #define MREGS_CHIPID1	0x10UL	/* Chip-ID, low bits              */
147 #define MREGS_CHIPID2	0x11UL	/* Chip-ID, high bits             */
154 #define MREGS_MPCNT	0x18UL	/* Missed Packet Count            */
156 #define MREGS_RPCNT	0x1aUL	/* Runt Packet Count              */
157 #define MREGS_RCCNT	0x1bUL	/* RX Collision Count             */
164 #define MREGS_TXFCNTL_DRETRY        0x80 /* Retry disable                  */
172 #define MREGS_TXFSTAT_ORETRY        0x08 /* TX 1 retry                     */
175 #define MREGS_TXFSTAT_RERROR        0x01 /* TX retry error                 */
178 #define MREGS_TXRCNT_CMASK          0x0f /* TX retry count                 */
188 #define MREGS_RXFSTAT_RBCNT         0x0f /* RX msg byte count              */
197 #define MREGS_IREG_RPKTCO           0x08 /* IRQ Runt packet count overflow */
217 #define MREGS_BCONFIG_RESET         0x01 /* SW-Reset the MACE              */
250 #define MREGS_PHYCONFIG_AUTO        0x04 /* Connector port auto-sel        */
294 #define NEXT_RX(num)       (((num) + 1) & (RX_RING_MAXSIZE - 1))
295 #define NEXT_TX(num)       (((num) + 1) & (TX_RING_MAXSIZE - 1))
296 #define PREV_RX(num)       (((num) - 1) & (RX_RING_MAXSIZE - 1))
297 #define PREV_TX(num)       (((num) - 1) & (TX_RING_MAXSIZE - 1))
300         (((qp)->tx_old <= (qp)->tx_new) ?                     \
301 	  (qp)->tx_old + (TX_RING_SIZE - 1) - (qp)->tx_new :  \
302 			    (qp)->tx_old - (qp)->tx_new - 1)
310 ((__u32)((unsigned long)(&(((struct qe_init_block *)0)->mem[elem]))))
332 ((__u32)((unsigned long)(&(((struct sunqe_buffers *)0)->mem[elem][0]))))
335 	void __iomem			*qcregs;		/* QEC per-channel Registers   */
336 	void __iomem			*mregs;		/* Per-channel MACE Registers  */