Lines Matching +full:rx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */
31 #define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */
34 #define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
48 #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */
49 #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */
50 #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */
53 #define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
96 * This register is used to perform a global reset of the RX and TX portions
97 * of the GEM asic. Setting the RX or TX reset bit will start the reset.
102 #define GREG_SWRST_RXRST 0x00000002 /* RX Software Reset */
130 * This 13-bit register is programmed by the driver to hold the descriptor
136 * This 13-bit register is updated by GEM to hold to descriptor entry index
148 #define TXDMA_CFG_ENABLE 0x00000001 /* Enable TX DMA channel */
159 #define TXDMA_CFG_PIOSEL 0x00000020 /* Enable TX FIFO PIO from cpu */
171 * them later. -DaveM
196 #define RXDMA_CFG 0x4000UL /* RX Configuration Register */
197 #define RXDMA_DBLOW 0x4004UL /* RX Descriptor Base Low */
198 #define RXDMA_DBHI 0x4008UL /* RX Descriptor Base High */
199 #define RXDMA_FWPTR 0x400CUL /* RX FIFO Write Pointer */
200 #define RXDMA_FSWPTR 0x4010UL /* RX FIFO Shadow Write Pointer */
201 #define RXDMA_FRPTR 0x4014UL /* RX FIFO Read Pointer */
202 #define RXDMA_PCNT 0x4018UL /* RX FIFO Packet Counter */
203 #define RXDMA_SMACHINE 0x401CUL /* RX State Machine Register */
205 #define RXDMA_DPLOW 0x4024UL /* RX Data Pointer Low */
206 #define RXDMA_DPHI 0x4028UL /* RX Data Pointer High */
207 #define RXDMA_KICK 0x4100UL /* RX Kick Register */
208 #define RXDMA_DONE 0x4104UL /* RX Completion Register */
209 #define RXDMA_BLANK 0x4108UL /* RX Blanking Register */
210 #define RXDMA_FADDR 0x410CUL /* RX FIFO Address */
211 #define RXDMA_FTAG 0x4110UL /* RX FIFO Tag */
212 #define RXDMA_DLOW 0x4114UL /* RX FIFO Data Low */
213 #define RXDMA_DHIT1 0x4118UL /* RX FIFO Data HighT0 */
214 #define RXDMA_DHIT0 0x411CUL /* RX FIFO Data HighT1 */
215 #define RXDMA_FSZ 0x4120UL /* RX FIFO Size */
217 /* RX Configuration Register. */
218 #define RXDMA_CFG_ENABLE 0x00000001 /* Enable RX DMA channel */
219 #define RXDMA_CFG_RINGSZ 0x0000001e /* RX descriptor ring size */
220 #define RXDMA_CFG_RINGSZ_32 0x00000000 /* - 32 entries */
221 #define RXDMA_CFG_RINGSZ_64 0x00000002 /* - 64 entries */
222 #define RXDMA_CFG_RINGSZ_128 0x00000004 /* - 128 entries */
223 #define RXDMA_CFG_RINGSZ_256 0x00000006 /* - 256 entries */
224 #define RXDMA_CFG_RINGSZ_512 0x00000008 /* - 512 entries */
225 #define RXDMA_CFG_RINGSZ_1K 0x0000000a /* - 1024 entries */
226 #define RXDMA_CFG_RINGSZ_2K 0x0000000c /* - 2048 entries */
227 #define RXDMA_CFG_RINGSZ_4K 0x0000000e /* - 4096 entries */
228 #define RXDMA_CFG_RINGSZ_8K 0x00000010 /* - 8192 entries */
229 #define RXDMA_CFG_RINGSZ_BDISAB 0x00000020 /* Disable RX desc batching */
232 #define RXDMA_CFG_FTHRESH 0x07000000 /* RX FIFO dma start threshold */
233 #define RXDMA_CFG_FTHRESH_64 0x00000000 /* - 64 bytes */
234 #define RXDMA_CFG_FTHRESH_128 0x01000000 /* - 128 bytes */
235 #define RXDMA_CFG_FTHRESH_256 0x02000000 /* - 256 bytes */
236 #define RXDMA_CFG_FTHRESH_512 0x03000000 /* - 512 bytes */
237 #define RXDMA_CFG_FTHRESH_1K 0x04000000 /* - 1024 bytes */
238 #define RXDMA_CFG_FTHRESH_2K 0x05000000 /* - 2048 bytes */
240 /* RX Descriptor Base Low/High.
243 * of the RX descriptor table. The 11 least significant bits are always
244 * zero. As a result, the RX descriptor table must be 2K aligned.
247 /* RX PAUSE Thresholds.
250 * GEM. The thresholds measure RX FIFO occupancy in units of 64 bytes.
255 /* RX Kick Register.
257 * This 13-bit register is written by the host CPU and holds the last
258 * valid RX descriptor number plus one. This is, if 'N' is written to
259 * this register, it means that all RX descriptors up to but excluding
262 * The hardware requires that RX descriptors are posted in increments
268 /* RX Completion Register.
270 * This 13-bit register is updated by GEM to indicate which RX descriptors
273 * updates this register value after the RX FIFO empties completely into
274 * the RX descriptor's buffer, but before the RX_DONE bit is set in the
278 /* RX Blanking Register. */
289 /* RX FIFO Size.
291 * This 11-bit read-only register indicates how large, in units of 64-bytes,
292 * the RX FIFO is. The driver uses this to properly configure the RX PAUSE
297 * them later. -DaveM
302 #define MAC_RXRST 0x6004UL /* RX MAC Software Reset Command*/
305 #define MAC_RXSTAT 0x6014UL /* RX MAC Status Register */
308 #define MAC_RXMASK 0x6024UL /* RX MAC Mask Register */
311 #define MAC_RXCFG 0x6034UL /* RX MAC Configuration Register*/
364 #define MAC_RXCVERR 0x6128UL /* RX code Violation Error Ctr */
369 #define MAC_TXRST_CMD 0x00000001 /* Start sw reset, self-clears */
371 /* RX MAC Software Reset Command. */
372 #define MAC_RXRST_CMD 0x00000001 /* Start sw reset, self-clears */
376 * Send_Pause and flow-control
395 /* RX MAC Status Register. */
410 /* The layout of the MAC_{TX,RX,C}MASK registers is identical to that
411 * of MAC_{TX,RX,C}STAT. Bits set in MAC_{TX,RX,C}MASK will prevent
414 * properly set the appropriate GREG_IMASK_{TX,RX,}MAC bits as well.
419 * NOTE: The TX MAC Enable bit must be cleared and polled until
424 * RX Carrier Extension 3) Set Slot Time to 0x200. This
425 * mode must be enabled when in half-duplex at 1Gbps, else
428 #define MAC_TXCFG_ENAB 0x00000001 /* TX MAC Enable */
431 #define MAC_TXCFG_EIPG0 0x00000008 /* Enable IPG0 */
439 /* RX MAC Configuration Register.
441 * NOTE: The RX MAC Enable bit must be cleared and polled until
444 * Similar rules apply to the Hash Filter Enable bit when
446 * Enable bit when programming the address filter registers.
448 #define MAC_RXCFG_ENAB 0x00000001 /* RX MAC Enable */
453 #define MAC_RXCFG_HFE 0x00000020 /* Hash Filter Enable */
454 #define MAC_RXCFG_AFE 0x00000040 /* Address Filter Enable */
456 #define MAC_RXCFG_RCE 0x00000100 /* RX Carrier Extension */
459 #define MAC_MCCFG_SPE 0x00000001 /* Send Pause Enable */
460 #define MAC_MCCFG_RPE 0x00000002 /* Receive Pause Enable */
468 #define MAC_XIFCFG_OE 0x00000001 /* MII TX Output Driver Enable */
469 #define MAC_XIFCFG_LBCK 0x00000002 /* Loopback TX to RX */
470 #define MAC_XIFCFG_DISE 0x00000004 /* Disable RX path during TX */
476 /* InterPacketGap0 Register. This 8-bit value is used as an extension
478 * timing of the RX-to-TX IPG. This value is ignored and presumed to
479 * be zero for TX-to-TX IPG calculations and/or when the Enable IPG0 bit
487 /* InterPacketGap1 Register. This 8-bit value defines the first 2/3
495 /* InterPacketGap2 Register. This 8-bit value defines the second 1/3
503 /* Slot Time Register. This 10-bit value specifies the slot time
510 /* Minimum Frame Size Register. This 10-bit register specifies the
522 * packets sent in half-duplex gigabit modes.
529 /* PA Size Register. This 10-bit register specifies the number of preamble
536 /* Jam Size Register. This 4-bit register specifies the duration of
542 /* Attempts Limit Register. This 8-bit register specifies the number
552 /* MAX Control Type Register. This 16-bit register specifies the
562 * ethernet MAC of the interface, 16-bits at a time. Register
582 * filter. The Address Filter 2&1 Mask Register denotes the 8-bit
584 * Filter 0 Mask Register denotes the 16-bit mask for the Address
592 /* Statistics Registers. All of these registers are 16-bits and
599 /* Random Number Seed Register. This 10-bit value is used as the
605 /* Pause Timer, read-only. This 16-bit timer is used to time the pause
607 * A non-zero value in this timer indicates that the MAC is currently in
612 #define MIF_BBCLK 0x6200UL /* MIF Bit-Bang Clock */
613 #define MIF_BBDATA 0x6204UL /* MIF Bit-Band Data */
614 #define MIF_BBOENAB 0x6208UL /* MIF Bit-Bang Output Enable */
621 /* MIF Bit-Bang Clock. This 1-bit register is used to generate the
623 * programmed in the "Bit-Bang" mode. Writing a '1' after a '0' into
630 /* MIF Bit-Bang Data. This 1-bit register is used to generate the
632 * is programmed in the "Bit-Bang" mode. The daa will be steered to the
637 /* MIF Big-Band Output Enable. THis 1-bit register is used to enable
638 * ('1') or disable ('0') the I-directional driver on the MII when the
639 * MIF is programmed in the "Bit-Bang" mode. The MDIO should be enabled
647 /* MIF Configuration Register. This 15-bit register controls the operation
651 #define MIF_CFG_POLL 0x00000002 /* Enable polling mechanism */
652 #define MIF_CFG_BBMODE 0x00000004 /* 1=bit-bang 0=frame mode */
654 #define MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */
655 #define MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */
658 /* MIF Frame/Output Register. This 32-bit register allows the host to
659 * communicate with a transceiver in frame mode (as opposed to big-bang
674 * operating in the poll mode. The poll status field is auto-clearing
680 /* MIF Mask Register. This 16-bit register is used when in poll mode
702 #define PCS_MIICTRL_RAN 0x00000200 /* Restart auto-neg, self clear */
705 #define PCS_MIICTRL_ANE 0x00001000 /* Auto-neg enable */
707 #define PCS_MIICTRL_WB 0x00004000 /* Wrapback, loopback at 10-bit
716 #define PCS_MIISTAT_ANA 0x00000008 /* Auto-neg Ability, always 1 */
718 #define PCS_MIISTAT_ANC 0x00000020 /* Auto-neg complete */
727 #define PCS_MIIADV_ACK 0x00004000 /* Read-only */
728 #define PCS_MIIADV_NP 0x00008000 /* Next-page, forced low */
741 #define PCS_CFG_JS 0x00000018 /* Jitter-study:
743 * 1 = high-frequency test pattern
744 * 2 = low-frequency test pattern
747 #define PCS_CFG_TO 0x00000020 /* 10ms auto-neg timer override */
749 /* PCS Interrupt Status Register. This register is self-clearing
758 #define PCS_DMODE_GMOE 0x00000008 /* GMII Output Enable */
764 #define PCS_SCTRL_LOOP 0x00000001 /* Loopback enable */
765 #define PCS_SCTRL_ESCD 0x00000002 /* Enable sync char detection */
769 #define PCS_SCTRL_PDWN 0x00000200 /* Software power-down */
788 #define BMCR_SPD2 0x0040 /* Gigabit enable? (bcm5411) */
806 /* MII BCM5400 1000-BASET Control register */
823 * control word. The same functionality is obtained via the TX-Kick
824 * and TX-Complete registers. As a result, GEM need not write back
839 #define TXDCTRL_CENAB 0x0000000020000000ULL /* CSUM Enable */
845 /* GEM requires that RX descriptors are provided four at a time,
846 * aligned. Also, the RX ring may not wrap around. This means that
848 * of the RX ring at all times.
854 * Unlike for TX, GEM does update the status word in the RX descriptors
856 * RX descriptors. It is advisory, GEM clears it but does not check
857 * it in any way. So when buffers are posted to the RX ring (via the
858 * RX Kick register) by the driver it must make sure the buffers are
861 * Even though GEM modifies the RX descriptors, it guarantees that the
871 #define RXDCTRL_TCPCSUM 0x000000000000ffffULL /* TCP Pseudo-CSUM */
880 ((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) | \
930 #define NEXT_TX(N) (((N) + 1) & (TX_RING_SIZE - 1))
931 #define NEXT_RX(N) (((N) + 1) & (RX_RING_SIZE - 1))
934 (((GP)->tx_old <= (GP)->tx_new) ? \
935 (GP)->tx_old + (TX_RING_SIZE - 1) - (GP)->tx_new : \
936 (GP)->tx_old - (GP)->tx_new - 1)
939 #define RX_BUF_ALLOC_SIZE(gp) ((gp)->rx_buf_sz + 28 + RX_OFFSET + 64)
981 unsigned int has_wol : 1; /* chip supports wake-on-lan */
1025 #define found_mii_phy(gp) ((gp->phy_type == phy_mii_mdio0 || gp->phy_type == phy_mii_mdio1) && \
1026 gp->phy_mii.def && gp->phy_mii.def->ops)