13 	u32 value = readl(ioaddr + XGMAC_DMA_MODE);  in dwxgmac2_dma_reset()
25 	u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);  in dwxgmac2_dma_init()
39 	u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));  in dwxgmac2_dma_init_chan()
55 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));  in dwxgmac2_dma_init_rx_chan()
71 	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));  in dwxgmac2_dma_init_tx_chan()
83 	u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);  in dwxgmac2_dma_axi()
139 		reg_space[i] = readl(ioaddr + i * 4);  in dwxgmac2_dma_dump_regs()
145 	u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));  in dwxgmac2_dma_rx_mode()
166 		u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));  in dwxgmac2_dma_rx_mode()
204 	value = readl(ioaddr + XGMAC_MTL_QINTEN(channel));  in dwxgmac2_dma_rx_mode()
211 	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));  in dwxgmac2_dma_tx_mode()
254 	u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));  in dwxgmac2_enable_dma_irq()
267 	u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));  in dwxgmac2_disable_dma_irq()
281 	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));  in dwxgmac2_dma_start_tx()
285 	value = readl(ioaddr + XGMAC_TX_CONFIG);  in dwxgmac2_dma_start_tx()
294 	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));  in dwxgmac2_dma_stop_tx()
298 	value = readl(ioaddr + XGMAC_TX_CONFIG);  in dwxgmac2_dma_stop_tx()
307 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));  in dwxgmac2_dma_start_rx()
311 	value = readl(ioaddr + XGMAC_RX_CONFIG);  in dwxgmac2_dma_start_rx()
320 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));  in dwxgmac2_dma_stop_rx()
328 	u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan));  in dwxgmac2_dma_interrupt()
329 	u32 intr_en = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));  in dwxgmac2_dma_interrupt()
374 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0);  in dwxgmac2_get_hw_feature()
390 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);  in dwxgmac2_get_hw_feature()
419 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);  in dwxgmac2_get_hw_feature()
431 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3);  in dwxgmac2_get_hw_feature()
474 	u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));  in dwxgmac2_enable_tso()
486 	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));  in dwxgmac2_qmode()
487 	u32 flow = readl(ioaddr + XGMAC_RX_FLOW_CTRL);  in dwxgmac2_qmode()
505 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));  in dwxgmac2_set_bfsize()
513 	u32 value = readl(ioaddr + XGMAC_RX_CONFIG);  in dwxgmac2_enable_sph()
519 	value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));  in dwxgmac2_enable_sph()
529 	u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));  in dwxgmac2_enable_tbs()
538 	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)) & XGMAC_EDSE;  in dwxgmac2_enable_tbs()